In some embodiments, radio-frequency amplifiers can include a plurality of narrow band power amplifiers implemented. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

A radio-frequency module including a module substrate having a first main surface and a second main surface on opposite sides; a low-noise amplifier disposed on the second main surface; and a power amplifier circuit in a Doherty configuration. The power amplifier including a first phase circuit; a second phase circuit; a carrier amplifier disposed on the first main surface and including an input terminal connected to a first end of the first phase circuit and an output terminal connected to a first end of the second phase circuit; and a peaking amplifier disposed on the first main surface and including an input terminal connected to a second end of the first phase circuit and an output terminal connected to a second end of the second phase circuit.

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

A power amplifier circuit includes a first impedance transformer circuit arranged to connect with a carrier device, and a second impedance transformer circuit arranged to connect with a peaking device. Both the first and the second impedance transformer circuit include a parallel impedance transformer arrangement.

A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

Disclosed is an electronic device comprising: a wireless communication circuit for generating an RF signal, an amplifier circuit electrically connected to the wireless communication circuit and configured to amplify the RF signal, and an antenna connected to the amplifier circuit. The amplifier circuit may comprise: a first amplifier; a second amplifier; a first transmission path connected to an output terminal of the first amplifier and the antenna; a second transmission path connected to an output terminal of the second amplifier and the first transmission path; a first variable impedance circuit located on the first transmission path and configured to change an electrical length of the first transmission path based on the frequency of the RF signal; and a second variable impedance circuit located on the second transmission path and configured to change the electrical length based on a power mode.

An amplifier (300) comprising: a first signal path comprising first amplifier circuitry (105A) configured to receive a first signal (RF1) with a frequency and a variable phase and amplitude at the frequency; a second signal path comprising second amplifier circuitry (105B) configured to receive a second signal (RF2) with the frequency, wherein at least one of the relative phase and amplitude of the second signal is fixed at the frequency; combiner circuitry (106) configured to combine an output of the first amplifier circuitry and the second amplifier circuitry.

An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element connected between the transistor output terminal and a quasi RF cold point node, a second inductive element connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes a third inductive element, a resistor, and a second capacitance in series between the quasi RF cold point node and the ground reference node and a third capacitance between a baseband termination circuit node and the ground reference node.

This application discloses example multi-phase-based Doherty power amplifier control methods and apparatus An example method includes obtaining a baseband signal and generating two vector signals based on the baseband signal, where the two vector signals each include a phase signal and amplitude signal, and the two vector signals are non-orthogonal signals. Amplitude control signals of a target power amplifier are obtained based on quantization encoding of amplitude signals of the two vector signals, where the target power amplifier includes a main and power amplifier, and the main and auxiliary power amplifier each include a plurality of working cells. Phase control signals of the target power amplifier are obtained based on phase signals of the two vector signals. Based on the phase control signals and the amplitude control signals, a plurality of working cells in the main power amplifier and the auxiliary power amplifier to output power signals are controlled.