H03F1/086

Amplitude control with signal swapping
10381992 · 2019-08-13 · ·

A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

Methods related to fast turn-on of radio-frequency amplifiers
10374559 · 2019-08-06 · ·

Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency amplifiers. In some embodiments, a method for amplifying a radio-frequency signal includes providing an amplification path implemented to amplify an radio-frequency signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the method includes providing a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

NEGATIVE FEEDBACK GAIN TRANSIMPEDANCE AMPLIFIER (TIA) SYSTEMS
20190238097 · 2019-08-01 ·

One embodiment describes a transimpedance amplifier (TIA) system. The system includes a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of an input current signal provided at the input node. The system also includes a negative feedback transformer coupled to the transistor to provide a negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor.

Regenerative current detection circuit, charge current detection circuit, and motor current detection system

A regenerative current detection circuit includes a first power MOS transistor that is configured as a current mirror to a second power MOS transistor connected to drive a motor winding, a first feedback amplifier that compares a first regenerative current that flows in the first power MOS transistor with a second regenerative current that flows in the second power MOS transistor and outputs a comparison result, the first regenerative current being obtained by multiplying the second regenerative current by a current mirror ratio, and a current detection circuit that outputs a detection current based on the comparison result.

SYSTEM AND METHOD FOR REDUCING OUTPUT HARMONICS

In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.

METHODS AND APPARATUS TO REDUCE OFFSET AND GAIN ERROR IN MULTISTAGE CURRENT SENSE AMPLIFIERS
20240178807 · 2024-05-30 ·

An example apparatus includes: a transconductance stage including: a fully differential amplifier configured to generate a differential current based on a voltage input; and a transistor configured to be controlled by an output of the fully differential amplifier and source current from an input of the fully differential amplifier; and a transimpedance stage coupled to the transconductance stage, the transimpedance stage including: resistor circuitry configured to convert the differential current into a differential voltage using a first resistance, a second resistance, and a third resistance; and a differential amplifier configured to convert the differential voltage to a single-ended voltage, which represents the voltage input.

AMPLIFIER WITH OUTPUT HARMONIC TERMINATION AND OUTPUT IMPEDANCE NETWORK
20240178803 · 2024-05-30 ·

An amplifier device may include an amplifier transistor and having harmonic termination circuitry and an output impedance network, such as an output T network, coupled to the output of the amplifier transistor. The amplifier device may be configured as an inverted F class amplifier having an operational frequency range with a center frequency of less than or equal to around 2.6 GHz. The harmonic termination circuitry and output impedance network may be configured to create a short circuit or near short circuit at the amplifier transistor output for third harmonic frequencies of the center frequency of the amplifier transistor and to create an open circuit or near open circuit at the amplifier transistor output for second harmonic frequencies of the center frequency. The output impedance network may be configured to increase the output impedance at the center frequency and reduce signal loss for the amplifier device.

Conversion circuit and detection circuit

A conversion circuit for converting a current signal into a first output voltage signal, where the current signal flows through a sensing component, is provided. The conversion circuit includes: a first current eliminating circuit, configured to eliminate a first current in the current signal. The first current eliminating circuit includes: a current sample and hold circuit; and a current driving circuit, coupled between the sensing component and the current sample and hold circuit; a second current eliminating circuit, coupled to the sensing component and configured to eliminate a second current in the current signal; and an integrating circuit, coupled to the sensing component and configured to integrate a third current in the current signal, and output a first input voltage signal between a first integration output terminal and a second integration output terminal.

Amplification circuit with split-length compensation scheme
10355656 · 2019-07-16 · ·

An amplification circuit includes: a current source; a first input transistor pair suitable for receiving a positive input voltage and having a split-length gate structure; a second input transistor pair suitable for receiving a negative input voltage and having a split-length gate structure; an enable unit suitable for supplying a current from the current source to each of the first input transistor pair and the second input transistor pair in response to an enable signal; a switching unit suitable for coupling a second split gate node between the second input transistor pair to a compensation capacitor node during an activation section of the enable signal; and a compensation driving unit suitable for compensating and driving a first split gate node between the first input transistor pair at an initial stage of the activation section of the enable signal.

Regulator amplifier circuit for outputting a fixed output voltage independent of a load current

A regulator amplifier circuit of an embodiment includes a differential amplifier circuit, an nMOS transistor, and a pMOS transistor. The differential amplifier circuit includes a differential circuit and a transistor. The differential circuit includes a differential MOS transistor circuit, and the transistor includes a gate voltage controlled by the differential circuit. The nMOS transistor includes a drain connected to a drain on minus side of the differential MOS transistor, and a gate connected to a source of the transistor. The nMOS transistor operates in a weak inversion region. The pMOS transistor includes a source connected to a source of the nMOS transistor, and a drain connected to a voltage lower than a source voltage of the nMOS transistor. The pMOS transistor operates in the weak inversion region.