A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal.

A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

A semiconductor IC includes a first radio-frequency element (e.g., an inductor in a low-noise amplifier), a second radio-frequency element (e.g., an inductor in a low-noise amplifier), a first via conductor (e.g., a via conductor that is placed between the first radio-frequency element and the second radio-frequency element and that is connected to a ground potential.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.

A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.

An RF power amplifier circuit includes a power divider, multiple power amplification circuits and a power combiner that cooperatively perform power amplification on an RF input signal so as to output an RF output signal, and an impedance conversion circuit that has a circuit terminal coupled to one of the power divider and the power combiner which has a microstrip structure, and that is configured such that a conversion impedance, which is an impedance seen into the impedance conversion circuit from the circuit terminal, matches an impedance seen into the power divider or the power combiner from the circuit terminal. The microstrip structure has a physical length associated with the conversion impedance.

A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.