An amplifier circuit includes an input terminal, an output terminal, an amplifier including a first transistor and a second transistor that are connected in parallel, a first capacitor, and a second capacitor, and an inductor. Each of the first transistor and the second transistor has a gate connected to the input terminal, a source connected to ground, and a drain connected to the output terminal. The inductor is provided between the input terminal and a node of parallel connection of the first transistor and the second transistor on the side of the input terminal. The first capacitor is arranged in a path connecting the node and the gate of the first transistor, the second capacitor is arranged in a path connecting the node and the gate of the second transistor, and the capacitance of the first capacitor differs from the capacitance of the second capacitor.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

A semiconductor integrated circuit includes an input terminal, an output terminal, and a multi-stage connection unit including multiple MOS transistors connected in multiple stages between the input terminal and the output terminal. The MOS transistors include an input stage transistor connected to the input terminal and an output stage transistor connected to the output terminal. A thickness of a gate dielectric of the output stage transistor is equal to a thickness of a gate dielectric of the input stage transistor, and a gate length of the output stage transistor is longer than a gate length of the input stage transistor.

A low noise amplifier includes: an amplification unit including a first transistor and a second transistor connected in a cascade structure and configured to amplify a signal input to a control terminal of the first transistor; and a gain controller connected between a contact point at which the first transistor and the second transistor are connected to each other and a power source voltage, and configured to adjust a gain of the amplification unit.

Examples of the disclosure include an amplifier system comprising an amplifier having an input to receive an input signal, and an output to provide an amplified output signal, the amplifier having a power level indicative of at least one of the input signal power and the amplified output signal power, and a linearizer coupled to the amplifier and having a plurality of modes of operation including a fully disabled mode and a fully enabled mode, the linearizer being configured to determine the power level of the amplifier, select a mode of operation of the plurality of modes of operation based on the power level of the amplifier, determine one or more linearization parameters corresponding to the selected mode of operation, and control linearization of the amplified output signal based on the determined one or more linearization parameters.

The present disclosure discloses a thin film transistor (TFT)-based bootstrap structure amplifier, and a chip. The amplifier includes an input circuit, an output buffer, and several bootstrap structure units. The bootstrap structure units include a TFT and a capacitor. The drain and the gate of the TFT are both connected to the same voltage node. The source of the TFT is connected to one end of the capacitor. The other end of the capacitor is connected to an output signal node. The output buffer is formed by connecting the sources and drains of several TFTs in series. Two ends of the output buffer are respectively connected to an input voltage node and an output signal node. The source of the TFT in each bootstrap structure unit is connected to the gates of the TFTs in one output buffer. The input circuit includes an input signal node, the output signal node, and a grounding node. The present disclosure can increase circuit gain and have a simple structure and low fabrication cost. The present disclosure can be widely applied to the field of integrated circuits.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

Amplification device and processes capable of miniaturization in a device for performing linear amplification and switching amplification operations on incoming signals are provided. The amplifying device includes a first amplifying unit for amplifying an input signal and outputting a first output signal, the input switch unit connected in parallel with the first amplifying unit for performing a switching operation by an input signal and outputting a switch output signal, and a second amplifying unit for amplifying a first output signal or a switch output signal and outputting a second output signal, and the first amplifying unit or the input switch unit operates based on the type of the input signal.