The present invention breaks up the frequency bands which can be filtered by a simple low-loss band-pass or low pass filter. The second harmonic frequency is reduced by use of a non-linear clipper element which controls the driving waveform symmetry and can reduce the harmonics by as much as 5-15db which makes the filter much simpler and allows the amplifier to remain wide-band. The output waveform from the amplifier is symmetrical or nearly symmetrical.

A linear amplifier is provided to have higher efficiency for an envelope tracking modulator. In one embodiment, a first stage amplifier circuit can be simply operated in a high gain mode or a high bandwidth mode for different applications, without using large chip area. In another embodiment, an output stage has a cascode structure whose dynamic range is controlled according to a voltage level of a supply voltage, to make a core device within the output stage have better protection and suitable dynamic range.

An operational amplifier based circuit has an operational amplifier, a feedback circuit, and a compensation circuit block. The feedback circuit is coupled between an output port and an input port of the operational amplifier. The compensation circuit block has circuits involved in stability compensation of the operational amplifier, wherein there is no stability compensation circuit driven at the output port of the operational amplifier.

The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.

Design of ultra broadband transimpedance amplifiers (TIA) for optical fiber communications is disclosed. In one embodiment, a TIA comprises a g.sub.m-boosted dual-feedback common-base stage, a level shifter and an RC-degenerated common-emitter stage, and a first emitter-follower stage, wherein the first emitter follower stage is inductively degenerated. An output of the TIA is buffered using a second emitter-follower stage.

The present invention breaks up the frequency bands which can be filtered by a simple low-loss band-pass or low pass filter. The second harmonic frequency is reduced by use of a non-linear clipper element which controls the driving waveform symmetry and can reduce the harmonics by as much as 5-15 db which makes the filter much simpler and allows the amplifier to remain wide-band. The output waveform from the amplifier is symmetrical or nearly symmetrical.

A circuit for amplifying a source signal generated by a signal source having a first impedance includes a transmission line transformer (TLT) having a first, a second, a third, and a fourth port wherein the TLT is coupled to receive the source signal at the first port and configured to output a corresponding impedance matched signal at the second port, the second port is coupled to the third port of the TLT, the circuit also including a TLT load having a first terminal coupled to the fourth port of the TLT and a second terminal coupled to a reference potential. The circuit additionally includes an amplifier device responsive to the impedance matched signal to generate an amplified signal.

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.

A Doherty amplifier used in a Z ohm based system is provided with a carrier amplifier, a peak amplifier, and an impedance transforming line for transforming the load of the carrier amplifier when an input signal is small. The impedance transforming line has a characteristic impedance lower than Z ohms and equal to the optimum load impedance of the carrier amplifier. The load of the Doherty amplifier is lower than Z ohms. A power amplifier that obtains large output power by combining output powers from a plurality of Doherty amplifiers by a power coupling circuit is constructed.

An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (M.sub.CG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (M.sub.CG1) further having a first source (112) coupled to the first input (102). A second transistor (M.sub.CS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (M.sub.CS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (M.sub.CS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (M.sub.CS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (M.sub.CG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (M.sub.CG2) further having a fourth source (132) coupled to the second input (104). A first load (Z.sub.L1) is coupled between the first output (106) and a second voltage rail (136). A second load (Z.sub.L2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L.sub.1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L.sub.2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (M.sub.CG1) is substantially equal to transconductance of the fourth transistor