The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

A semiconductor device includes: a channel layer; a barrier layer that is provided above the channel layer and includes indium aluminum gallium nitride (InAlGaN); a first insulating layer provided on the barrier layer; and a second insulating layer provided on the first insulating layer, wherein the first insulating layer is a silicon nitride layer that includes one or more types of group III elements included in the barrier layer.

A semiconductor device includes first and second transistors on a substrate of first conductivity type, and a well region between at least one of the first and second transistors and the substrate, and has second conductivity type different from first conductivity type. The first transistor includes a first channel layer on the substrate, a first barrier layer on the first channel layer, a first gate electrode on the first barrier layer, and a first source electrode and a first drain electrode on opposite sides of the first gate electrode, and connected to the first channel layer. The second transistor includes a second channel layer on the substrate, a second barrier layer on the second channel layer, a second gate electrode on the second barrier layer, and a second source electrode and a second drain electrode on opposite sides of the second gate electrode, and connected to the second channel layer.

A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.