A microphone system includes a microphone and a pre-amplification conditioning circuit configured within a housing and comprising a pair of matched JFETs configured in a differential pair with common-source configuration and, when biased, are operable to receive and amplify the differential microphone output signal. The microphone further includes a pair of BJTs configured as a complimentary feedback transistor pair with each of the pair of BJTs coupled in parallel to a corresponding one of the pair of matched JFETs, and a current sink coupled to the matched JFETs and corresponding emitter electrodes of the BJTs and operable to maintain a fixed total direct current through each of the matched JFETs and BJTs, which reduces the JFETs corresponding electrical load, reduces signal noise, and increases a maximum amplified microphone output signal level at the drains of the matched JFETs.

An amplifying circuit, comprising: a charging circuit, comprising a plurality of first transistors electrically coupled to a target device; and an output circuit, comprising a plurality of second transistors electrically coupled to the target device. After at least one of the first transistors turns on and the second transistors turn off such that the charging circuit charges the target device to a predetermined voltage, at least one of the first transistors and at least one of the second transistors simultaneously turn on for a predetermined time, and then at least one of the second transistors turns on but the first transistors turns off.

An amplifying circuit, comprising: a charging circuit, comprising a plurality of first transistors electrically coupled to a target device; and an output circuit, comprising a plurality of second transistors electrically coupled to the target device. After at least one of the first transistors turns on and the second transistors turn off such that the charging circuit charges the target device to a predetermined voltage, at least one of the first transistors and at least one of the second transistors simultaneously turn on for a predetermined time, and then at least one of the second transistors turns on but the first transistors turns off.

A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.

This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

An audio system includes a variable voltage power supply and at least one remotely positioned speaker assembly. The speaker assembly includes a driver (e.g., a tweeter) and a switching amplifier. Moving the switching amplifier to a remote position within the speaker assembly provides numerous design advantages and allows for utilization of a smaller power supply. In addition, the audio system is configured to detect a type of the at least one speaker and to adjust an output voltage of the variable voltage power supply accordingly. This allows for reconfiguration and/or expansion of original systems. A related method of detecting a type of speaker electrically connected to an audio source is also provided.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.