An audio amplifier has an analog current source amplifier and a class D amplifier. The analog current source amplifier is active in a first mode to drive a speaker when an audio signal has smaller amplitude. The class D amplifier is active in a second mode to drive the speaker when the audio signal has larger amplitude. Other aspects are also described and claimed.

A class-D amplifier according to an embodiment includes a PWM modulator, a first output transistor group that includes two transistors complementarily operating and includes a first connection point between the two transistors as an output terminal, a second output transistor group that includes two transistors complementarily operating and includes a second connection point between the two output transistors as an output terminal, and a selector configured to selectively provide a PWM pulse signal to one of the first output transistor group and the second output transistor group. A system that includes the second output transistor group, a low-pass filter, and a load connected to the low-pass filter configures a series resonance circuit.

A class-D amplifier according to an embodiment includes a PWM modulator, a first output transistor group that includes two transistors complementarily operating and includes a first connection point between the two transistors as an output terminal, a second output transistor group that includes two transistors complementarily operating and includes a second connection point between the two output transistors as an output terminal, and a selector configured to selectively provide a PWM pulse signal to one of the first output transistor group and the second output transistor group. A system that includes the second output transistor group, a low-pass filter, and a load connected to the low-pass filter configures a series resonance circuit.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

A first system includes first and second buck-boost amplifiers. The first amplifier is connected to a battery, includes a first inductor and a first plurality of switches connected to the first inductor, and drives first and second loads. The second amplifier is connected to the battery, includes a second inductor and a second plurality of switches connected to the second inductor, and drives the first and second loads. A controller drives the first and second plurality of switches to operate each of the first and second amplifiers in a single inductor multiple output mode. A second system includes multiple buck-boost amplifiers connected to a battery and driving respective loads. Each amplifier includes inductors and switches connected to the inductors. A controller drives the switches to utilize one or more inductors based on an amount of power used by each amplifier to drive the respective loads.

An audio system has an amplifier having first and second power stages configurable to drive a speaker, each power stage having two transistors connected in series. Each of one or more analog-to-digital converters is connected to measure a corresponding voltage drop across a corresponding transistor. A processor is connected to characterize the operation of the audio system based on the measured voltage drops. The ADC(s) and the processor can be used during start-up and/or run-time operations of the audio system to determine or detect transistor ON resistance, system lag time, speaker current, open-load faults, shorted-load faults, and short-to-Vdd/Vss faults. To avoid errors, the processor determines or detects and avoids under-drive conditions, high-frequency conditions, ripple-current periods, and lag-time periods while characterizing the system operations.

A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

A signal modulator for modulating at least one input signal is disclosed. The modulator includes an adaptive ramp generator receiving a clock signal having a clock cycle. The adaptive ramp generator provides a ramp signal having a profile starting from a minimum level adjusted in each clock cycle. The signal modulator may receive a first, second, and third input signal, and a clock signal. The first and second input signals may derive from a single signal where the second signal is equal to the first signal shifted by 180 degrees. The third signal may be a fixed level that sets the nominal duty cycle of the modulator. The input signal having the highest amplitude among the first, second, and third input signals is identified. The minimum level of the ramp signal is adjusted, and the peak value of the ramp maintained substantially equal to the signal having the highest amplitude.

An amplifier circuit with in-band gain degradation compensation is shown. The amplifier circuit has an input-stage amplifier, at least one intermediate-stage amplifier, and an output-stage amplifier cascaded between an input port and an output port of the amplifier circuit. A compensation capacitor is coupled between the output port of the amplifier circuit and an output port of the input-stage amplifier. A high-order damping circuit is coupled to an output port of the intermediate-stage amplifier.