In some embodiments, an audio amplifier can include an input node for receiving a digital signal, and a controller coupled to the input node through a feed-forward path. The controller can be configured to generate a driving signal based on the digital signal. The audio amplifier can further include a driver configured to provide an amplified signal at an output node based on the driving signal, and a feedback circuit that couples the output node of the driver to the controller. The feedback circuit can be configured to provide a feedback signal for comparison with a reference signal representative of the digital signal to generate an error signal, such that the feedback circuit provides a form of the error signal to the controller for adjustment of the digital signal.

In some embodiments, an audio driver includes an audio amplifier configured to operate in a high output resistance (HOR) mode with an HOR driver or a zero output resistance (ZOR) mode with a ZOR driver, The audio amplifier includes an output node coupled to both of the HOR driver and the ZOR driver, such that the output node is subject to an effect of the ZOR driver in a disabled state when the audio amplifier is operating in the HOR mode. The audio driver further includes a control system configured to correct for the effect of the disabled ZOR driver by adjusting an input signal.

A differential delta-sigma-modulator has an integrator including a pair of single-ended amplifiers. A sample clock is driving a first switchable capacitor configuration and a second switchable capacitor configuration at a predetermined switching cycle. The first switchable capacitor configuration is adapted for sampling respective outputs from the pair of single-ended amplifiers on a pair of output sampling capacitors in the first part of the switching cycle. The second switchable capacitor configuration is adapted for charging a common mode capacitor with the average voltage of the voltage sampled by the pair of output sampling capacitors in the second part of the switching cycle. The voltage across the common mode capacitor represents the common mode voltage for the integrator.

A differential delta-sigma-modulator has an integrator including a pair of single-ended amplifiers. A sample clock is driving a first switchable capacitor configuration and a second switchable capacitor configuration at a predetermined switching cycle. The first switchable capacitor configuration is adapted for sampling respective outputs from the pair of single-ended amplifiers on a pair of output sampling capacitors in the first part of the switching cycle. The second switchable capacitor configuration is adapted for charging a common mode capacitor with the average voltage of the voltage sampled by the pair of output sampling capacitors in the second part of the switching cycle. The voltage across the common mode capacitor represents the common mode voltage for the integrator.

The present invention discloses an audio processing circuit, wherein when the audio processing circuit determines that a signal being processed is a small signal, an output stage uses a regulated supply voltage provided by a voltage regulator, and the output stage uses an open-loop structure to reduce noise of an output audio signal; and when the audio processing circuit determines that the signal being processed is a large signal, the output stage directly uses the supply voltage without using the regulated supply voltage, and the output stage uses a closed-loop structure to reduce the total harmonic distortion of the output audio signal. By using the present invention, the audio processing circuit can have a good performance indicator with a small chip area design.

This application relates to driver circuitry (200) for receiving a digital input signal (D) and outputting, at first and second output nodes (203p, 203n), first and second analogue driving signals respectively for driving a transducer (101), e.g. loudspeaker, in a bridge-tied-load configuration. The driver circuitry may particularly be suitable for driving low-impedance transducers. The driver circuitry has first and second digital-to-analogue converters (201p, 201n) configured to receive the digital input signal and the outputs of the first and second digital-to-analogue converters are coupled to the first and second output nodes respectively. A differential-output amplifier circuit (202) has outputs connected to the first and second output nodes and is configured to regulate the outputs of the digital-to-analogue converters at output nodes to provide the analogue driving signals.

An audio signal reproduction apparatus includes a temperature detection unit detecting a temperature of a battery pack, a voltage detection unit detecting a voltage of the battery pack, and a control unit performing an output control on a basis of temperature information detected by the temperature detection unit and voltage information detected by the voltage detection unit.

Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.