Methods related to power amplification systems with adjustable common base bias. A method of implementing a power amplification system can include providing a cascode amplifier coupled to a radio-frequency input signal and coupled to a radio-frequency output. The method can further include providing a biasing component configured to apply one or more biasing signals to the cascode amplifier, the biasing component including a bias controller and one or more bias components. Each respective bias component may be coupled to a respective bias transistor.

Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal and a bias control circuit that biases the power amplifier. The power amplifier includes an amplification transistor that receives the RF signal at an input, and a first bias network and a second bias network each connected to the input. The bias control circuit includes a first switch, a first reference current source that provides the first reference current to the first bias network through the first switch, a second switch, and a second reference current source that provides the second reference current to the second bias network through the second switch.

Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

A network interface device includes a passive path between an entry port and a first port. The network interface device also includes an active path between the entry port and a second port. The network interface device also includes a buffer in the active path configured to absorb, attenuate, terminate, or isolate radio-frequency (RF) signals. The network interface device also includes a switching element in the active path configured to cause the RF signals to bypass the buffer when the network interface is in a first state that exists during powered operation of the network interface device, and direct the RF signals to the buffer when the network interface device is in a second state that exists during non-powered operation or faulted operation of the network interface device.

A network interface device includes a passive path between an entry port and a first port. The network interface device also includes an active path between the entry port and a second port. The network interface device also includes a buffer in the active path configured to absorb, attenuate, terminate, or isolate radio-frequency (RF) signals. The network interface device also includes a switching element in the active path configured to cause the RF signals to bypass the buffer when the network interface is in a first state that exists during powered operation of the network interface device, and direct the RF signals to the buffer when the network interface device is in a second state that exists during non-powered operation or faulted operation of the network interface device.

Certain aspects of the present disclosure are directed to an amplifier. The amplifier may include a transistor coupled to an output of the amplifier, and a resonator coupled between the output of the amplifier and a reference potential node, a resonant frequency of the resonator being set to be at a subharmonic of a fundamental frequency of the amplifier, and an impedance of the resonator being greater than a load impedance of the amplifier at the fundamental frequency of the amplifier.

In one embodiment, an impedance matching network includes a variable reactance circuit having fixed reactance components and corresponding switching circuits. Each switching circuit includes a diode and a driver circuit. The driver circuit includes, coupled in series, a biasing current source positioned to provide a bias current to bias the diode, a first switch, a second switch, and a resistor. For each diode of each switching circuit, the control circuit is configured to receive a value related to a voltage drop on the resistor and, based on the value related to the voltage drop, adjust the bias current being provided by the biasing current source.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.