An example process includes reducing a quality factor of a first tunable bandpass filter, used, for example, in a low-noise amplifier stage of a polar receiver. A first wideband test signal centered at a desired center frequency of a second tunable bandpass filter is received. A frequency response of the second tunable bandpass filter to the first wideband test signal is estimated using a Fast Fourier Transform (FFT) signal processor. At least a resonant frequency or a quality factor of the second tunable bandpass filter are calibrated based at least in part on a portion of the estimated frequency response of the second tunable bandpass filter obtained from the FFT signal processor. Frequency response characteristics of the first tunable bandpass filter may be similarly tuned in accordance with the example process.

An example process includes reducing a quality factor of a first tunable bandpass filter, used, for example, in a low-noise amplifier stage of a polar receiver. A first wideband test signal centered at a desired center frequency of a second tunable bandpass filter is received. A frequency response of the second tunable bandpass filter to the first wideband test signal is estimated using a Fast Fourier Transform (FFT) signal processor. At least a resonant frequency or a quality factor of the second tunable bandpass filter are calibrated based at least in part on a portion of the estimated frequency response of the second tunable bandpass filter obtained from the FFT signal processor. Frequency response characteristics of the first tunable bandpass filter may be similarly tuned in accordance with the example process.

Methods and apparatus to determine automated gain control parameters for an automated gain control protocol are disclosed. An example apparatus includes a first tuner to amplify an audio signal. Disclosed example apparatus also include a second tuner to amplify the audio signal. Disclosed example apparatus also include a first controller to tune the first tuner to apply a first gain representative of a first range of gains to the audio signal to determine a first amplified audio signal and tune the second tuner to apply a second gain representative a second range of gains to the audio signal to determine a second amplified audio signal, the second range of gains lower than the first range of gains. Disclosed example apparatus also include a second controller to select the first range of gains to be utilized in an automated gain control protocol when the first gain results in clipping of the first amplified audio signal and the second gain does not result in clipping of the second amplified audio signal.

A carrier aggregation method can include amplifying a first signal with a first current converter to generate a current representative of the amplified first signal, and amplifying a second signal with a second current converter to generate a current representative of the amplified second signal. The method can further include processing the amplified first signal and the amplified second signal with an adder circuit, with the first current converter and the adder circuit forming a first cascode amplifier, and the second current converter and the adder circuit forming a second cascode amplifier. The method can further include providing an output signal at a common output node that is coupled to an output of each of the first and second cascode amplifiers.

A carrier aggregation method can include amplifying a first signal with a first current converter to generate a current representative of the amplified first signal, and amplifying a second signal with a second current converter to generate a current representative of the amplified second signal. The method can further include processing the amplified first signal and the amplified second signal with an adder circuit, with the first current converter and the adder circuit forming a first cascode amplifier, and the second current converter and the adder circuit forming a second cascode amplifier. The method can further include providing an output signal at a common output node that is coupled to an output of each of the first and second cascode amplifiers.

Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal, a power management circuit that controls a voltage level of a supply voltage of the power amplifier, and a bias control circuit that biases the power amplifier. The power management circuit is operable in multiple supply control modes, such as an average power tracking (APT) mode and an envelope tracking (ET) mode. The bias control circuit is configured to switch a bias of the power amplifier based on the supply control mode of the power management circuit.

A bias circuit includes a bias current circuit and a temperature compensation circuit. The bias current circuit includes a first resistor and a first transistor, in a first current path connected between a current terminal of a reference current and a ground, and connected to each other in series, and a second transistor in a second current path connected between the current terminal and the ground, and having a base connected to a collector of the first transistor. The temperature compensation circuit includes a second resistor in the second current path, and connected between an emitter of the second transistor and a base of the first transistor and having a first thermal coefficient, and a third resistor included in the second current path, and connected between the base of the first transistor and the ground and having a second thermal coefficient, different from the first thermal coefficient.

Embodiments of a device and method are disclosed. In an embodiment, an RF amplifier includes first and second RF signal paths having RF input interfaces, RF output interfaces, and corresponding transistors connected between the respective RF input interfaces and RF output interfaces, wherein control terminals of the transistors are connected to the RF input interfaces and current conducting terminals of the transistors are connected to the corresponding RF output interfaces. The RF amplifier including a conductive path between the current conducting terminal of the first transistor and the current conducting terminal of the second transistor, wherein the conductive path includes a first inductance, a second inductance, and a capacitance electrically connected between the first inductance and the second inductance.

A high frequency amplifier 1 includes an input terminal P.sub.IN, an output terminal P.sub.OUT, a transistor 5 configured to amplify an RF signal applied to the input terminal P.sub.IN, a matching circuit 9 for a fundamental of the RF signal and a reflection circuit 7 for a harmonic relative to the fundamental, the matching circuit 9 and the reflection circuit 7 being connected in series between the transistor 5 and the output terminal P.sub.OUT, an extraction circuit 13 configured to extract a harmonic appearing at the output terminal P.sub.OUT, processing circuits 15, 17 configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit 13, and a multiplexing circuit 19 configured to multiplex the harmonic processed by the processing circuits 15, 17 to the harmonic reflected by the reflection circuit 7 and give the multiplexed harmonic to the transistor 5.

An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.