The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

A method and system for power amplifier tuning based on an automobile audio bus (A2B) interface including determining a plurality of tuning paths and a plurality of tuning parameters of one or more power amplifiers; determining data volumes of the plurality of tuning parameters according to the type(s) of the one or more power amplifiers; determining a data volume for each tuning path according to the data volumes of the plurality of tuning parameters; allocating the number of A2B channels to each tuning path according to the data volume determined for each tuning path; calculating a tuning speed for each tuning, path according to the number of A2B channels allocated to each tuning path; and allocating the calculated tuning speed for each tuning path to the one or more power amplifiers through the A2B interface.

A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I.sub.0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Methods and apparatus to determine automated gain control parameters for an automated gain control protocol are disclosed. An example apparatus includes a first tuner to amplify an audio signal. Disclosed example apparatus also include a second tuner to amplify the audio signal. Disclosed example apparatus also include a first controller to tune the first tuner to apply a first gain representative of a first range of gains to the audio signal to determine a first amplified audio signal and tune the second tuner to apply a second gain representative a second range of gains to the audio signal to determine a second amplified audio signal, the second range of gains lower than the first range of gains. Disclosed example apparatus also include a second controller to select the first range of gains to be utilized in an automated gain control protocol when the first gain results in clipping of the first amplified audio signal and the second gain does not result in clipping of the second amplified audio signal.

A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal T.sub.IN installed on one side of a wiring substrate 3, an output terminal T.sub.OUT installed on the other side of the wiring substrate 3, and gate bias terminals T.sub.1G and T.sub.2G and drain bias terminals T.sub.1D and T.sub.2D installed at positions with the input terminal T.sub.IN and the output terminal T.sub.OUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal T.sub.IN and the output terminal T.sub.OUT.

A high frequency amplification circuit includes transmission amplification circuits 11 and 12; a transmission filter D-Tx whose pass band is a band D of a first frequency band group; transmission filters E-Tx and G-Tx whose pass bands are respectively bands E and G of a second frequency band group; an output matching circuit 31 configured to match the transmission amplification circuit 11 and the transmission filter D-Tx; and an output matching circuit 32 configured to match the transmission amplification circuit 12 and the transmission filters E-Tx and G-Tx. The band D is positioned at a high frequency-side end portion of the first frequency band group, and the band E is positioned at a low frequency-side end portion of the second frequency band group. The output matching circuit 31 includes a low-pass circuit, and the output matching circuit 32 includes an impedance-variable circuit.

A high frequency amplification circuit includes transmission amplification circuits 11 and 12; a transmission filter D-Tx whose pass band is a band D of a first frequency band group; transmission filters E-Tx and G-Tx whose pass bands are respectively bands E and G of a second frequency band group; an output matching circuit 31 configured to match the transmission amplification circuit 11 and the transmission filter D-Tx; and an output matching circuit 32 configured to match the transmission amplification circuit 12 and the transmission filters E-Tx and G-Tx. The band D is positioned at a high frequency-side end portion of the first frequency band group, and the band E is positioned at a low frequency-side end portion of the second frequency band group. The output matching circuit 31 includes a low-pass circuit, and the output matching circuit 32 includes an impedance-variable circuit.

A power amplifier circuit includes a first transistor having a base or gate connected to a signal path, an emitter or source grounded via a first conductor, and a collector or drain, the first transistor amplifying an input signal supplied to the base or gate thereof along the signal path and outputting the amplified signal from the collector or drain thereof; a first element in a preceding stage of the first transistor, the first element having a first end connected to the signal path such that the first element is connected along a path branched from the signal path, and a second end grounded via a second conductor; and a first capacitor having a first end connected to a node between the emitter or source of the first transistor and the first conductor, and a second end connected to a node between the first element and the second conductor.

A power amplifier circuit includes a first transistor having a base or gate connected to a signal path, an emitter or source grounded via a first conductor, and a collector or drain, the first transistor amplifying an input signal supplied to the base or gate thereof along the signal path and outputting the amplified signal from the collector or drain thereof; a first element in a preceding stage of the first transistor, the first element having a first end connected to the signal path such that the first element is connected along a path branched from the signal path, and a second end grounded via a second conductor; and a first capacitor having a first end connected to a node between the emitter or source of the first transistor and the first conductor, and a second end connected to a node between the first element and the second conductor.

A power amplifier circuit includes a first transistor that amplifies an RF signal; a bias current source that supplies a bias current to a second terminal of the first transistor through a first current path; and an adjustment circuit that adjusts the bias current in accordance with a variable power-supply voltage supplied from a power-supply terminal. The adjustment circuit includes first to third resistors, and an adjustment transistor including a first terminal connected to the power-supply terminal through the first resistor, a second terminal connected to the bias current source through the second resistor, and a third terminal connected to the first current path through the third resistor. When the variable power-supply voltage is not less than a first voltage and not greater than a third voltage, the adjustment circuit increases a current that flows to the power-supply terminal through a second current path as the variable power-supply voltage decreases.