Switchless carrier aggregation. In some embodiments, a carrier aggregation circuit can include a first filter configured to allow operation in a first frequency band, and a second filter configured to allow operation in a second frequency band. The circuit can further include a first signal path implemented between the first filter and an output node, with the first signal path including a plurality of amplification stages configured to amplify a first signal. The first signal path can be substantially free of switches. The circuit can further include a second signal path implemented between the second filter and the output node, with the second signal path including a plurality of amplification stages configured to amplify a second signal. The second signal path can be substantially free of switches.

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor.

Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.

Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.

Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal, a power management circuit that controls a voltage level of a supply voltage of the power amplifier, and a bias control circuit that biases the power amplifier. The power management circuit is operable in multiple supply control modes, such as an average power tracking (APT) mode and an envelope tracking (ET) mode. The bias control circuit is configured to switch a bias of the power amplifier based on the supply control mode of the power management circuit.

A hybrid multiplexer includes a filter configured to allow a high-frequency signal of an HB to pass therethrough, and a filter configured to allow a high-frequency signal of an MB to pass therethrough, in which the filter includes a matching circuit, a first resonance circuit defined by one of an LPF and an HPF, and a second resonance circuit defined by the other of the LPF and the HPF, the LPF includes an inductor and a parallel arm resonator, the HPF includes a serial arm resonator and an inductor, and a resonant frequency of the parallel arm resonator and an anti-resonant frequency of the serial arm resonator are both located between a frequency at a low-band end of the HB and a frequency at a high-band end of the HB.

A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I.sub.0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

A power amplifier circuit includes a first transistor, a second transistor and a bias circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connecting to a collector of the first transistor and a collector configured to output a second signal. The bias circuit is coupled to the first transistor and the second transistor. The bias circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor about twice a DC voltage at the collector of the first transistor. The bias circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor about twice an AC or RF voltage at the collector of the first transistor.