A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.

An electronic device may include wireless circuitry with a processor that generates baseband signals, an upconversion circuit that upconverts the baseband signals to radio-frequency signals, a power amplifier, an antenna, and a transmit filter with a frequency dependent filter response coupled between the output of the power amplifier and the antenna. To help mitigate the frequency dependent filter response, the wireless circuitry may further include predistortion circuitry having an amplifier load response estimator that implements a baseband model of the filter response, an amplifier non-linearity estimator that models the non-linear behavior of the amplifier, and a control signal generator for adjusting the power amplifier based on the output of the amplifier load response estimator and the amplifier non-linearity estimator.

An adjustable gain power amplifier, a gain adjustment method and a mobile terminal are disclosed. The adjustable gain power amplifier comprises an input matching circuit, a gain adjustment circuit, a biasing circuit, a main amplification circuit, and an output matching circuit; the input matching circuit is connected between an input end and the gain adjustment circuit; the gain adjustment circuit is connected between the input matching circuit and the input end of the main amplification circuit; the output end of the main amplification circuit is connected to the output matching circuit, a positive power source end thereof is connected to a power supply source, a negative power source end thereof is connected to the biasing circuit; the biasing circuit provides different biasing voltages for the main amplification circuit; and the gain adjustment circuit and the biasing circuit are respectively connected to a gain adjustment control voltage (Vctrl).

To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a variable current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region.

To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a variable current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region.

An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor (Q.sub.1); a second transistor (Q.sub.2); and a third transistor (Q.sub.3), wherein: the first (Q.sub.1), second (Q.sub.2) and third (Q.sub.3) transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

A power amplifier circuit includes a Doherty amplifier including a divider that divides a first signal into a second signal and a third signal, a carrier amplifier that amplifies the second signal and outputs a fourth signal, a peak amplifier that amplifies the third signal and outputs a fifth signal, a combiner that combines the fourth signal and the fifth signal and outputs an amplified signal of the first signal, a first bias circuit that supplies a first bias current or voltage to the carrier amplifier, and a second bias circuit that supplies a second bias current or voltage corresponding to a control signal to the peak amplifier; and a control circuit that supplies the control signal corresponding to a level of the second signal to the second bias circuit. The control circuit includes a detecting unit, an output unit, and a filter circuit.

A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.