The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.

Circuits and methods for 2G amplification using 3G/4G linear path combination. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Circuits and methods for 2G amplification using 3G/4G linear path combination. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Disclosed herein is a diversity receiver (DRx) configuration configured to support carrier aggregation. The DRx configuration includes a diversity receiver (DRx) module coupled to a diversity radio frequency (DRF) module. The DRx module includes a splitter and a combiner to provide a plurality of DRx paths for signals of different frequency bands. The DRx modules includes a plurality of DRx amplifiers for individual frequency bands and the DRF module includes a plurality of downstream amplifiers. A controller is configured to adjust a gain of the DRF amplifiers in response to changes in a gain of the amplifiers of the DRx module.

Disclosed herein is a diversity receiver (DRx) configuration configured to support carrier aggregation. The DRx configuration includes a diversity receiver (DRx) module coupled to a diversity radio frequency (DRF) module. The DRx module includes a splitter and a combiner to provide a plurality of DRx paths for signals of different frequency bands. The DRx modules includes a plurality of DRx amplifiers for individual frequency bands and the DRF module includes a plurality of downstream amplifiers. A controller is configured to adjust a gain of the DRF amplifiers in response to changes in a gain of the amplifiers of the DRx module.

Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.

Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.

Aspects of this disclosure relate to efficient power amplifiers, such as class-F power amplifiers. A power amplifier transistor can provide an amplified RF signal. A termination can be coupled to an output of the power amplifier transistor and configured to provide a short circuit at a second harmonic. In some instances, the termination circuit can provide an open circuit at a third harmonic. A resonant circuit can be coupled to the output terminal of the power amplifier transistor and configured to provide an open circuit at the third harmonic. In certain embodiments, an input termination circuit coupled to an input terminal of the power amplifier transistor can provide a short circuit at the second harmonic. The power amplifiers of this disclosure can be implemented, for example, in envelope tracking applications.

Aspects of this disclosure relate to efficient power amplifiers, such as class-F power amplifiers. A power amplifier transistor can provide an amplified RF signal. A termination can be coupled to an output of the power amplifier transistor and configured to provide a short circuit at a second harmonic. In some instances, the termination circuit can provide an open circuit at a third harmonic. A resonant circuit can be coupled to the output terminal of the power amplifier transistor and configured to provide an open circuit at the third harmonic. In certain embodiments, an input termination circuit coupled to an input terminal of the power amplifier transistor can provide a short circuit at the second harmonic. The power amplifiers of this disclosure can be implemented, for example, in envelope tracking applications.

A power amplification module includes: a first bipolar transistor in which a radio frequency signal is input to a base and an amplified signal is output from a collector; a second bipolar transistor that is thermally coupled with the first bipolar transistor and that imitates operation of the first bipolar transistor; a third bipolar transistor in which a first control voltage is supplied to a base and a first bias current is output from an emitter; a first resistor that generates a third control voltage corresponding to a collector current of the second bipolar transistor at a second terminal; and a fourth bipolar transistor in which a power supply voltage is supplied to a collector, the third control voltage is supplied to a base, and a second bias current is output from an emitter.