Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

Compression control through amplitude adjustment of a radio frequency input signal. A power amplifier module can include a power amplifier. The power amplifier can include a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a power amplifier bias controller. The power amplifier bias controller can include a current comparator, a saturation controller, and a radio frequency (RF) attenuator. The current comparator can be configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The saturation controller can be configured to supply a reference signal to the RF attenuator based on the comparison value. The RF attenuator can be configured to modify the amplitude of an RF input signal supplied to the power amplifier based at least in part on the reference signal.

Compression control through amplitude adjustment of a radio frequency input signal. A power amplifier module can include a power amplifier. The power amplifier can include a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a power amplifier bias controller. The power amplifier bias controller can include a current comparator, a saturation controller, and a radio frequency (RF) attenuator. The current comparator can be configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The saturation controller can be configured to supply a reference signal to the RF attenuator based on the comparison value. The RF attenuator can be configured to modify the amplitude of an RF input signal supplied to the power amplifier based at least in part on the reference signal.

A bias circuit for applying bias current to a low quiescent current amplifier includes first and second transistors and a transistor pair circuit. The first transistor is connected to a supply bias voltage source and an auxiliary bias voltage source, and is controlled by a bias voltage output from the auxiliary bias voltage source, the first transistor acting as a current source. The second transistor is connected to the supply bias voltage source and an output of the first transistor, and is controlled by the output of the first transistor to selectively buffer supply bias current from the supply bias voltage source provided to the low quiescent current amplifier via a bias resistor. The transistor pair circuit includes third and fourth transistors connected in series, one of the third and fourth transistors is also connected in parallel with a dividing resistor, the transistor pair circuit acting as a voltage source.

A bias circuit for applying bias current to a low quiescent current amplifier includes first and second transistors and a transistor pair circuit. The first transistor is connected to a supply bias voltage source and an auxiliary bias voltage source, and is controlled by a bias voltage output from the auxiliary bias voltage source, the first transistor acting as a current source. The second transistor is connected to the supply bias voltage source and an output of the first transistor, and is controlled by the output of the first transistor to selectively buffer supply bias current from the supply bias voltage source provided to the low quiescent current amplifier via a bias resistor. The transistor pair circuit includes third and fourth transistors connected in series, one of the third and fourth transistors is also connected in parallel with a dividing resistor, the transistor pair circuit acting as a voltage source.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.

A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.