Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system that may include a telecommunications satellite. Embodiments include “chained” feedback-regulated voltage supply circuits. These circuits substantially eliminate the need for separate regulator circuits for each regulated voltage. These circuits are designed to automatically maintain a substantially constant first voltage at a first node for a first load and maintain a substantially constant second voltage at a second node for a second load. Some disclosed configurations of these circuits may be useful to achieve greater current capability at the same voltage without requiring larger switches and higher inductor and capacitor sizes that may be needed in a single (conventional) stage voltage supply circuit.

A balun configured for a power range between 500 W and 5 kW output includes a balanced signal port comprising a first connection and a second connection and further includes a single-ended signal port comprising a third connection and a fourth connection, the fourth connection being connected to ground. In addition, the balun includes a first capacitor disposed between the first connection and a first end of a first resistor and a second capacitor disposed between the second connection and the first end of the first resistor. A second end of the first resistor is connected to ground.

A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

When a potential difference V.sub.1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage V.sub.th, a protection circuit (13) starts an operation to reduce the potential difference V.sub.1 such that the potential difference V.sub.1 is smaller than the threshold voltage V.sub.th. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.

When a potential difference V.sub.1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage V.sub.th, a protection circuit (13) starts an operation to reduce the potential difference V.sub.1 such that the potential difference V.sub.1 is smaller than the threshold voltage V.sub.th. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

A supply circuit providing transmission of a control signal to gate leg by a power transistor. The supply circuit includes a primary transistor, a primary resistance connected between the primary transistor drain leg and ground; a secondary resistant connected to supply leg of primary transistor on one side and to gate leg, the primary transistor and a power supply from other side; a secondary transistor connected to drain leg of primary transistor from gate leg, connected to ground from drain leg and connected to the power supply by means of a third resistance from supply leg and a control signal output connected to the secondary transistor supply leg, providing transmission of a control signal by power transistor to a gate leg.

A supply circuit providing transmission of a control signal to gate leg by a power transistor. The supply circuit includes a primary transistor, a primary resistance connected between the primary transistor drain leg and ground; a secondary resistant connected to supply leg of primary transistor on one side and to gate leg, the primary transistor and a power supply from other side; a secondary transistor connected to drain leg of primary transistor from gate leg, connected to ground from drain leg and connected to the power supply by means of a third resistance from supply leg and a control signal output connected to the secondary transistor supply leg, providing transmission of a control signal by power transistor to a gate leg.