Linearity is improved in an amplifier circuit without lowering gain.

The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.

Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.

Monolithic microwave integrated circuits are provided that include a substrate, a transmit/receive selection device that is formed on the substrate, a high power amplifier formed on the substrate and coupled to a first RF port of the transmit/receive selection device, a low noise amplifier formed on the substrate and coupled to a second RF port of the transmit/receive selection device and a protection circuit that is coupled to a first control port of the transmit/receive selection device.

Monolithic microwave integrated circuits are provided that include a substrate, a transmit/receive selection device that is formed on the substrate, a high power amplifier formed on the substrate and coupled to a first RF port of the transmit/receive selection device, a low noise amplifier formed on the substrate and coupled to a second RF port of the transmit/receive selection device and a protection circuit that is coupled to a first control port of the transmit/receive selection device.

Antenna impedance prediction via power amplifier parameter. In some embodiments, a power amplification system can include a splitter circuit and a combiner circuit, and first and second Doherty power amplifiers implemented in a quadrature configuration between the splitter circuit and the combiner circuit, with each Doherty power amplifier including a carrier amplifier and a peaking amplifier. The power amplification system can further include a monitoring circuit configured to measure at least some of base currents associated with the carrier and peaking amplifiers of the first and second Doherty power amplifiers, and generate a signal capable of adjusting a load impedance presented to an output of the combiner circuit.

A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.

A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.