Patent classifications
H03F3/193
Power amplifier circuit
The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.
Power amplifier circuit
The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.
Power amplifier circuit
A power amplifier circuit includes a first transistor, wherein a radio frequency signal is inputted to a base or gate of the first transistor; a second transistor having an emitter connected to a collector or drain of the first transistor, wherein a first voltage is supplied to a collector of the second transistor, and a first amplified signal obtained by amplifying the radio frequency signal is outputted from the collector of the second transistor; and a third transistor configured to supply a bias voltage to a base of the second transistor. A second voltage is supplied to a collector or drain of the third transistor, a third voltage corresponding to the first voltage is supplied to a base or gate of the third transistor, and the bias voltage, which corresponds to the third voltage, is supplied from an emitter or source of the third transistor.
Wideband Amplifier Circuit
An amplifier includes a first coil coupled to at least one input node. The amplifier further includes second and third coils. A first terminal of the second coil is coupled to a source terminal of a first transistor, while a second terminal of the second coil is coupled to a source terminal of a second transistor. A third coil includes first and second terminals coupled to gate terminals of the first and second transistors, respectively. Responsive to receiving an input signal, the first coil electromagnetically conveys the signal to the second and third coils.
Method and device for selectively supplying voltage to multiple amplifiers by using switching regulators
Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.
Method and device for selectively supplying voltage to multiple amplifiers by using switching regulators
Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.
Receiver with broadband low-noise amplifier and filter bypass
A receiver front end is provided with a bypass mode of operation in which a received carrier-aggregated RF signal bypasses a bandpass filter to drive a broadband low-noise amplifier. The low-noise amplifier amplifies the carrier-aggregated RF signal to form an amplified RF signal.
WIDE BAND DOHERTY POWER AMPLIFIER
A wideband power amplifier is presented. The wideband power amplifier configured to be coupled to a load having an impedance Z.sub.L, where the wideband power amplifier comprises: a quadrature coupler; a carrier amplifier coupled to the quadrature coupler; a peak amplifier coupled to the quadrature coupler; wherein the carrier amplifier saturates at an input power level lower than the input power level at which the peak amplifier saturates; wherein each of the carrier amplifier and the peak amplifier has a termination impedance of approximately R.sub.opt, where R.sub.opt is the optimum impedance at which the carrier amplifier and the peak amplifier will deliver rated max powers; a impedance transformer, coupled to the carrier amplifier having a characteristic impedance of 2*R.sub.opt; an impedance transformer, coupled to the peak amplifier and the impedance transformer; wherein the impedance transformer is configured transform a load impedance Z.sub.L to 2*R.sub.opt.
WIDE BAND DOHERTY POWER AMPLIFIER
A wideband power amplifier is presented. The wideband power amplifier configured to be coupled to a load having an impedance Z.sub.L, where the wideband power amplifier comprises: a quadrature coupler; a carrier amplifier coupled to the quadrature coupler; a peak amplifier coupled to the quadrature coupler; wherein the carrier amplifier saturates at an input power level lower than the input power level at which the peak amplifier saturates; wherein each of the carrier amplifier and the peak amplifier has a termination impedance of approximately R.sub.opt, where R.sub.opt is the optimum impedance at which the carrier amplifier and the peak amplifier will deliver rated max powers; a impedance transformer, coupled to the carrier amplifier having a characteristic impedance of 2*R.sub.opt; an impedance transformer, coupled to the peak amplifier and the impedance transformer; wherein the impedance transformer is configured transform a load impedance Z.sub.L to 2*R.sub.opt.
AMPLIFICATION DEVICE
An amplification device includes an amplification circuit, an inductor, a regulator, and a impedance circuit. The amplification circuit has an input terminal for receiving a radio frequency signal, and an output terminal for outputting an amplified radio frequency signal. The inductor has a first terminal, and a second terminal coupled to the output terminal of the amplification circuit. The regulator is coupled to the first terminal of the inductor and generates a steady voltage and/or a steady current. The impedance circuit has a first terminal coupled to the output terminal of the amplification circuit, and a second terminal coupled to a first system voltage terminal. The impedance circuit provides a low frequency impedance path to suppress a beat frequency signal in the amplified radio frequency signal.