A differential power amplifier (DPA) includes an p-side and a n-side half circuit. The p-side and n-side half circuits include an p-side and n-side base, which receive respective in-phase and out-of-phase signals of a differential signal. The DPA includes an p-side biasing circuit and a n-side biasing circuit. The p-side and n-side biasing circuit are configured to provide a controllable p-side and n-side biasing signal to the p-side and n-side base, respectively. The DPA includes a power source which provides positive DC voltage to the controller of the p-side and n-side half circuits. The DPA includes supply and grounding circuit structure which provides common mode DC paths and balances the n-side and p-side half circuits to provide a radio frequency (RF) virtual ground to an emitter of the n-side half circuit and p-side half circuit.

A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

An exemplary embodiment of a low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 40 GHz-60 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. An auxiliary amplifier amplifies the same inputs and generates an amplified signal and amplified noise both being out of phase relative to the inputs. A summation circuit combines all of these amplified signals with the noise being cancelled since the auxiliary amplifier provides the same amount of amplification as the amplifier and the amplified noise signals being summed are 180 degrees out of phase to each other. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

A high-frequency amplifier circuitry includes a capacitor, a first transistor, a second transistor, and an ESD. The capacitor has one end connected to an input node. The first transistor has a gate connected to another end of the capacitor, and has a source grounded via an inductor. The second transistor is cascode-connected with the first transistor, has a gate grounded in a high-frequency manner, and outputs from a drain thereof a signal made by amplifying a signal output from a drain of the first transistor. The ESD protection circuitry includes a plurality of PN junction diodes, has a first terminal connected to the input node, has a second terminal grounded, and has a third terminal connected to the source of the first transistor.

A high-frequency amplifier circuitry includes a capacitor, a first transistor, a second transistor, and an ESD. The capacitor has one end connected to an input node. The first transistor has a gate connected to another end of the capacitor, and has a source grounded via an inductor. The second transistor is cascode-connected with the first transistor, has a gate grounded in a high-frequency manner, and outputs from a drain thereof a signal made by amplifying a signal output from a drain of the first transistor. The ESD protection circuitry includes a plurality of PN junction diodes, has a first terminal connected to the input node, has a second terminal grounded, and has a third terminal connected to the source of the first transistor.

A balancing circuit which may compensate for bandwidth attenuation introduced by interference between signals includes an amplifying circuit, a rising edge detection circuit and/or a falling edge detection circuit. By means of detecting the rising/falling edge of an original signal, the resulting pulse signal contains the phase information of a single 0 bit and a single 1 bit in the original signal, thus the phase of a rising edge or the phase of a falling edge of the original signal may be compensated respectively, so as to compensate for the high-frequency attenuation caused by interference between signals.

A balancing circuit which may compensate for bandwidth attenuation introduced by interference between signals includes an amplifying circuit, a rising edge detection circuit and/or a falling edge detection circuit. By means of detecting the rising/falling edge of an original signal, the resulting pulse signal contains the phase information of a single 0 bit and a single 1 bit in the original signal, thus the phase of a rising edge or the phase of a falling edge of the original signal may be compensated respectively, so as to compensate for the high-frequency attenuation caused by interference between signals.

A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.