An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

A variable gain circuit includes: input/output terminals P1 and P2 configured to input/output a high frequency signal; a transistor having a signal terminal a connected to the input/output terminal P1, a signal terminal b connected to the input/output terminal P2, and a control terminal; bias terminals B1, B2 and B3, and a reference voltage terminal respectively set to a first variable voltage, a second variable voltage, a third variable voltage, and a fixed voltage that are independent of one another; an impedance element connected between the bias terminal B1 and the signal terminal a; an impedance element connected between the bias terminal B2 and the signal terminal b; an impedance element connected between the bias terminal B3 and the control terminal; and a first switch configured to switch between connecting and not connecting the reference voltage terminal and the control terminal.

A variable gain circuit includes: input/output terminals P1 and P2 configured to input/output a high frequency signal; a transistor having a signal terminal a connected to the input/output terminal P1, a signal terminal b connected to the input/output terminal P2, and a control terminal; bias terminals B1, B2 and B3, and a reference voltage terminal respectively set to a first variable voltage, a second variable voltage, a third variable voltage, and a fixed voltage that are independent of one another; an impedance element connected between the bias terminal B1 and the signal terminal a; an impedance element connected between the bias terminal B2 and the signal terminal b; an impedance element connected between the bias terminal B3 and the control terminal; and a first switch configured to switch between connecting and not connecting the reference voltage terminal and the control terminal.

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a full amplitude mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a half amplitude mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a full amplitude mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a half amplitude mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.