An amplifier apparatus (332) comprises a main linear amplifier sub-circuit (402) having a main driving signal input terminal (331) and a main amplifier output terminal (406). The apparatus also comprises an auxiliary linear amplifier sub-circuit (404) having an auxiliary driving signal input terminal (357) and an auxiliary amplifier output terminal (408). A combining network (410) is operably coupled between the main amplifier output terminal (406) and the auxiliary amplifier output terminal (408), the combining network (410) having a main-side terminal (424) and an auxiliary-side terminal (434). The main linear amplifier sub-circuit (402) is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal (331). The auxiliary linear amplifier sub-circuit (404) is arranged to generate, when in use, an impedance modifying signal at the auxiliary-side terminal (357) in response to an auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit (402) generates the main amplified signal, the auxiliary linear amplifier sub-circuit (404) also being arranged to amplify substantially more than half of each wave cycle of the auxiliary driving signal.

An amplifier apparatus (332) comprises a main linear amplifier sub-circuit (402) having a main driving signal input terminal (331) and a main amplifier output terminal (406). The apparatus also comprises an auxiliary linear amplifier sub-circuit (404) having an auxiliary driving signal input terminal (357) and an auxiliary amplifier output terminal (408). A combining network (410) is operably coupled between the main amplifier output terminal (406) and the auxiliary amplifier output terminal (408), the combining network (410) having a main-side terminal (424) and an auxiliary-side terminal (434). The main linear amplifier sub-circuit (402) is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal (331). The auxiliary linear amplifier sub-circuit (404) is arranged to generate, when in use, an impedance modifying signal at the auxiliary-side terminal (357) in response to an auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit (402) generates the main amplified signal, the auxiliary linear amplifier sub-circuit (404) also being arranged to amplify substantially more than half of each wave cycle of the auxiliary driving signal.

An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

Apparatus and methods for low noise amplifiers (LNAs) are provided herein. In certain configurations, an LNA includes a mode control circuit that operates the LNA in one of a plurality of modes including a gain mode and a bypass mode, a gain circuit electrically connected between an input terminal and an output terminal and operable to amplify a radio frequency signal received from the input terminal in the gain mode, and a bypass circuit electrically connected between the input terminal and the output terminal and operable to bypass the gain circuit in the bypass mode. The bypass circuit includes a balun that provides a first amount of compensation for a difference in phase delay between the bypass circuit and the gain circuit, and the LNA further includes a phase compensation circuit operable to provide a second amount of compensation for the difference in phase delay.

Apparatus and methods for low noise amplifiers (LNAs) are provided herein. In certain configurations, an LNA includes a mode control circuit that operates the LNA in one of a plurality of modes including a gain mode and a bypass mode, a gain circuit electrically connected between an input terminal and an output terminal and operable to amplify a radio frequency signal received from the input terminal in the gain mode, and a bypass circuit electrically connected between the input terminal and the output terminal and operable to bypass the gain circuit in the bypass mode. The bypass circuit includes a balun that provides a first amount of compensation for a difference in phase delay between the bypass circuit and the gain circuit, and the LNA further includes a phase compensation circuit operable to provide a second amount of compensation for the difference in phase delay.

A receiver includes a passive CTLE (continuous-time linear equalizer) configured to receive a first voltage signal from a first node and output a current signal to a second node in accordance with a first control signal; a CG (common-gate) amplifier configured to receive the current signal and output a second voltage signal at a third node in accordance with a second control signal; a first active inductor configured to provide an inductive load at the third node; a CS (common-source) CTLE configured to receive the second voltage signal and output a third voltage signal at a fourth node in accordance with a third control signal; a second active inductor configured to provide an inductive load at the fourth node; and a decision circuit configured to receive the third voltage signal and output a decision in accordance with a clock signal.

A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.

A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.

An inductor circuit includes first inductive circuit, second inductive circuit, and third inductive circuit. First inductive circuit at receiver side has a first end coupled to a first port of an antenna and a second end coupled to an input port of a receiving circuit. Second inductive circuit at transmitter side has a first end and a second end respectively coupled to output ports of a power amplifier. Third inductive circuit at antenna side has a first end coupled to a first port of the antenna and having a second end. Second inductive circuit and the third inductive circuit are disposed on an outer ring to form a ring shape and the third inductive circuit is disposed on an inner ring within the outer ring to form a spiral shape. Third inductive circuit is disposed between the second inductive circuit and the first inductive circuit.