A power amplifier that can support multiple communication networks while maintaining power efficiency across each of the supported communication networks is disclosed. In some implementations described herein, a power amplifier module includes a bypass circuit that enables different voltage supplies to be provided to the power amplifier. By regulating the voltage supply provided to the power amplifier, the power amplifier can support different communication networks while maintaining power efficiency across a dynamic frequency range. Moreover, embodiments herein may include a buck converter, or other form of DC-DC converter, that enables the power amplifier to operate with respect to multiple communication networks. Advantageously, in certain embodiments, because wireless devices that include multiple power amplifiers often require a DC-DC converter to support at least some of the communication networks, the inclusion of the buck converter in the embodiments described herein does not add additional cost or size to the wireless device.

A power amplifier that can support multiple communication networks while maintaining power efficiency across each of the supported communication networks is disclosed. In some implementations described herein, a power amplifier module includes a bypass circuit that enables different voltage supplies to be provided to the power amplifier. By regulating the voltage supply provided to the power amplifier, the power amplifier can support different communication networks while maintaining power efficiency across a dynamic frequency range. Moreover, embodiments herein may include a buck converter, or other form of DC-DC converter, that enables the power amplifier to operate with respect to multiple communication networks. Advantageously, in certain embodiments, because wireless devices that include multiple power amplifiers often require a DC-DC converter to support at least some of the communication networks, the inclusion of the buck converter in the embodiments described herein does not add additional cost or size to the wireless device.

A non-linear high-frequency amplifier arrangement suitable for generating power outputs 1 kW at frequencies of 1 MHz for plasma excitation is provided. The arrangement includes two LDMOS transistors each connected by their source connection to aground connection point, where the LDMOS transistors have the same design and are arranged in an assembly, a power transformer whose primary winding is connected to drain connections of the LDMOS transistors, a signal transformer whose secondary winding is connected by a first end to a gate connection of one LDMOS transistor and by a second end to a gate connection of the other LDMOS transistor, and a feedback path from the drain connection to the gate connection of each of the LDMOS transistors.

A non-linear high-frequency amplifier arrangement suitable for generating power outputs 1 kW at frequencies of 1 MHz for plasma excitation is provided. The arrangement includes two LDMOS transistors each connected by their source connection to aground connection point, where the LDMOS transistors have the same design and are arranged in an assembly, a power transformer whose primary winding is connected to drain connections of the LDMOS transistors, a signal transformer whose secondary winding is connected by a first end to a gate connection of one LDMOS transistor and by a second end to a gate connection of the other LDMOS transistor, and a feedback path from the drain connection to the gate connection of each of the LDMOS transistors.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

Radio frequency (RF) amplifiers, such as power amplifiers, are provided herein. In certain configurations, an RF amplifier includes an input terminal that receives an RF input signal, an output terminal that provides an RF output signal, an injection-locked oscillator driver stage that amplifies the RF input signal to generate an injection-locked RF signal, and a stacked output stage that further amplifies the injection-locked RF signal to generate the RF output signal. The stacked output stage includes a stack of at least a first transistor and a second transistor in series with one another. Thus, the stacked output stage is operable over a wide range of supply voltage to overcome the relatively low breakdown voltages of scaled transistors. Moreover, the injection-locked oscillator driver stage provides the RF amplifier with excellent power efficiency, including in applications in which the stacked output stage operates with a supply voltage that is variable.

Radio frequency (RF) amplifiers, such as power amplifiers, are provided herein. In certain configurations, an RF amplifier includes an input terminal that receives an RF input signal, an output terminal that provides an RF output signal, an injection-locked oscillator driver stage that amplifies the RF input signal to generate an injection-locked RF signal, and a stacked output stage that further amplifies the injection-locked RF signal to generate the RF output signal. The stacked output stage includes a stack of at least a first transistor and a second transistor in series with one another. Thus, the stacked output stage is operable over a wide range of supply voltage to overcome the relatively low breakdown voltages of scaled transistors. Moreover, the injection-locked oscillator driver stage provides the RF amplifier with excellent power efficiency, including in applications in which the stacked output stage operates with a supply voltage that is variable.

This disclosure provides systems and apparatuses for reducing flicker noise in output signals provided by a radio frequency (RF) amplifier. In some implementations, the RF amplifier may include a bias generator to provide one or more bias signals to control operating points of devices and circuits of the RF amplifier. The bias generator may include a feedback circuit to generate a current to attenuate flicker noise within the bias generator. In some implementations, the feedback circuit may receive a bias voltage and may generate the current based on a frequency of the bias voltage.

The present invention concerns a programmable power amplifier comprising:

an amplifier core transistor circuit connected to an amplifier output node; a switch connected to the amplifier core transistor circuit, the switch being configured to switch on and off the amplifier core transistor circuit; and a feedback circuit of the amplifier core transistor circuit. The feedback circuit comprises a digital-to-analog converter and an operational amplifier having a first input node configured to receive a first reference signal; a second input node connected to the digital-to-analog converter; and an output node for outputting an operational amplifier output signal and connected to the amplifier core transistor circuit for controlling the amount of current flowing in the amplifier core transistor circuit. The digital-to-analog converter has a programmable resistance value for controlling the resistance of the digital-to-analog converter to thereby adjust a digital-to-analog converter output signal fed to the second input node of the operational amplifier for controlling an amplifier output signal at the amplifier output node.