Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

Examples disclosed herein relate to a vector modulator architecture, having an input splitter network configured to receive a radio frequency (RF) input signal and generate a plurality of quadrature signals at different phases, a variable gain amplifier (VGA) stage coupled to the input splitter network and configured to apply a first gain to one or more of the plurality of quadrature signals, a power combiner coupled to the VGA stage and configured to combine the plurality of quadrature signals into a combined RF signal, and a power amplifier (PA) stage coupled to the power combiner and configured to apply a second gain to the combined RF signal and generate an output RF signal. Other examples disclosed herein relate to an antenna system for autonomous vehicles and a radar system for use in an autonomous driving vehicle.

Examples disclosed herein relate to a vector modulator architecture, having an input splitter network configured to receive a radio frequency (RF) input signal and generate a plurality of quadrature signals at different phases, a variable gain amplifier (VGA) stage coupled to the input splitter network and configured to apply a first gain to one or more of the plurality of quadrature signals, a power combiner coupled to the VGA stage and configured to combine the plurality of quadrature signals into a combined RF signal, and a power amplifier (PA) stage coupled to the power combiner and configured to apply a second gain to the combined RF signal and generate an output RF signal. Other examples disclosed herein relate to an antenna system for autonomous vehicles and a radar system for use in an autonomous driving vehicle.

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.

Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.

A receiver front end having low noise amplifiers (LNAs) with enhanced input third order intercept point is disclosed herein. A cascode having a common source configured input FET and a common gate configured load FET have a degeneration circuit comprising a tank circuit tuned to a harmonic of the operating frequency.

A receiver front end having low noise amplifiers (LNAs) with enhanced input third order intercept point is disclosed herein. A cascode having a common source configured input FET and a common gate configured load FET have a degeneration circuit comprising a tank circuit tuned to a harmonic of the operating frequency.