Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier.

Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier.

A multi-stage device includes multiple stages such as a first stage and a second stage. During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. The transistor component is controlled to derive the output signal from the intermediate signal inputted to the circuit path.

A amplifier device includes an amplifier, a coupling circuit, and a filter circuit. The amplifier amplifies a high frequency signal, and outputs to signal output ports the high frequency signal. The coupling circuit is provided side-by-side with the amplifier in a first direction on a substrate, connected to the signal output ports, and configured to couple output signals and output one output signal to an output terminal. The filter circuit is provided on the substrate and connected to the coupling circuit, and configured to reduce third-order IMD included in the one output signal. The one output signal is output from a middle of the substrate in a second direction intersecting with the first direction, and the filter circuit is arranged next to an edge of the substrate in the second direction, and arranged next to an edge of the substrate on the output terminal side in the first direction.

A amplifier device includes an amplifier, a coupling circuit, and a filter circuit. The amplifier amplifies a high frequency signal, and outputs to signal output ports the high frequency signal. The coupling circuit is provided side-by-side with the amplifier in a first direction on a substrate, connected to the signal output ports, and configured to couple output signals and output one output signal to an output terminal. The filter circuit is provided on the substrate and connected to the coupling circuit, and configured to reduce third-order IMD included in the one output signal. The one output signal is output from a middle of the substrate in a second direction intersecting with the first direction, and the filter circuit is arranged next to an edge of the substrate in the second direction, and arranged next to an edge of the substrate on the output terminal side in the first direction.

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

An apparatus (e.g., an imaging system) includes a circuit, including: a p-i-n diode having a cathode coupled to a cathode bias voltage or ground; a charge transistor having a first source/drain terminal coupled to an anode of the diode; a storage capacitor having a first terminal coupled to a second source/drain terminal of the charge transistor and a second terminal coupled to the cathode; an amplification transistor having a gate terminal coupled to the first terminal of the storage capacitor and a first source/drain terminal coupled to a reference voltage; a read transistor having a first source/drain terminal coupled to a second source/drain terminal of the amplification transistor; a data line having a first terminal coupled to a second source/drain terminal of the read transistor; and a readout circuit coupled to a second terminal of the data line, providing an output voltage corresponding to charge on the storage capacitor.

An apparatus (e.g., an imaging system) includes a circuit, including: a p-i-n diode having a cathode coupled to a cathode bias voltage or ground; a charge transistor having a first source/drain terminal coupled to an anode of the diode; a storage capacitor having a first terminal coupled to a second source/drain terminal of the charge transistor and a second terminal coupled to the cathode; an amplification transistor having a gate terminal coupled to the first terminal of the storage capacitor and a first source/drain terminal coupled to a reference voltage; a read transistor having a first source/drain terminal coupled to a second source/drain terminal of the amplification transistor; a data line having a first terminal coupled to a second source/drain terminal of the read transistor; and a readout circuit coupled to a second terminal of the data line, providing an output voltage corresponding to charge on the storage capacitor.

Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.