A power amplifier system comprises an envelope tracker configured to generate a supply voltage that changes in relation to an envelope of a radio frequency signal, a power amplifier configured to amplify the radio frequency signal, and an adaptation circuit configured to adapt the supply voltage to provide operating power to the power amplifier. The adaptation circuit includes at least one Gallium Nitride field-effect-transistor configured to generate the operating power in response to an increased swing of the supply voltage and at least one linearizing circuit configured to linearize an operation of the Gallium Nitride field-effect-transistor.

A radio-frequency (RF) splitter is provided. The RF splitter includes a common branch node configured to transfer an RF signal, input from an input port, to at least one of first and second output ports, first and second branch nodes electrically connected between the common branch node and the first and second output ports, first and second series switches configured to control switching operations to electrically connect the common branch node and the first and second branch nodes to each other, first and second inductors electrically connected between the common branch node and the first and second branch nodes, a resistor electrically connected between the first and second branch nodes, and first and second shunt switches configured to control switching operations to electrically connect the first and second branch nodes and the resistor to each other.

A hybrid diode silicon on insulator front end module and related method are provided. The front end module includes a transmit branch that includes a transmit circuit and a receive branch that includes a receive circuit. The receive circuit includes a low noise amplifier, a pin diode including an anode and a cathode; and a switch. The anode of the pin diode is operatively connected to an antenna switch port and an input voltage source. The cathode of the pin diode is operatively connected to a cathode of the switch. Turning on the switch facilitates a drainage of residual electrical current at the pin diode.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplification circuit includes: a power supply terminal that is connected to a power supply; a first transistor that has a first source terminal, a first drain terminal, and a first gate terminal to which a high-frequency signal is inputted; a second transistor that has a second source terminal that is connected to the first drain terminal, a second drain terminal that outputs a high frequency signal, and a second gate terminal that is grounded; a capacitor that is serially arranged on a second path that connects the second gate terminal and the power supply terminal; and a switch that is serially arranged on a first path, which connects the second drain terminal and the power supply terminal, or the second path. The second drain terminal and the second gate terminal are connected to each other via the switch and the capacitor.

An amplification circuit includes: a power supply terminal that is connected to a power supply; a first transistor that has a first source terminal, a first drain terminal, and a first gate terminal to which a high-frequency signal is inputted; a second transistor that has a second source terminal that is connected to the first drain terminal, a second drain terminal that outputs a high frequency signal, and a second gate terminal that is grounded; a capacitor that is serially arranged on a second path that connects the second gate terminal and the power supply terminal; and a switch that is serially arranged on a first path, which connects the second drain terminal and the power supply terminal, or the second path. The second drain terminal and the second gate terminal are connected to each other via the switch and the capacitor.

A high frequency amplifier includes a first transistor and a second transistor, a first drain pad connected to the first transistor and a second drain pad connected to the second transistor, a matching circuit pattern having a first transmission line connected to the first drain pad and a second transmission line connected to the second drain pad, a first wire and a second wire, and a wiring pattern connected to the first drain pad via the first transmission line and the first wire and connected to the second drain pad via the second transmission line and the second wire. An effective impedance of the second wire is larger than an effective impedance of the first wire. The matching circuit pattern has an asymmetrical external shape. An electrical length of the second transmission line is shorter than an electrical length of the first transmission line.

A high frequency amplifier includes a first transistor and a second transistor, a first drain pad connected to the first transistor and a second drain pad connected to the second transistor, a matching circuit pattern having a first transmission line connected to the first drain pad and a second transmission line connected to the second drain pad, a first wire and a second wire, and a wiring pattern connected to the first drain pad via the first transmission line and the first wire and connected to the second drain pad via the second transmission line and the second wire. An effective impedance of the second wire is larger than an effective impedance of the first wire. The matching circuit pattern has an asymmetrical external shape. An electrical length of the second transmission line is shorter than an electrical length of the first transmission line.

Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.