An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.

A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

An amplification unit contains two or more sets containing a plurality of amplification circuits, and amplifies power of an RF (Radio Frequency) signal. A combining unit contains two or more combiners corresponding to the two or more sets, combines RF signals output by the amplification circuits, and outputs a resultant RF signal. The amplification unit has one chassis storing each amplification circuit. The amplification unit and the combining unit have two or more connectors which are arranged transversely. The amplification unit and the combining unit are attachable/detachable.

An amplification unit contains two or more sets containing a plurality of amplification circuits, and amplifies power of an RF (Radio Frequency) signal. A combining unit contains two or more combiners corresponding to the two or more sets, combines RF signals output by the amplification circuits, and outputs a resultant RF signal. The amplification unit has one chassis storing each amplification circuit. The amplification unit and the combining unit have two or more connectors which are arranged transversely. The amplification unit and the combining unit are attachable/detachable.

A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.

An amplifying apparatus includes a variable gain amplifying circuit configured to operate in a gain mode selected from a plurality of gain modes in response to a first control signal during operation in an amplification mode, a variable attenuation circuit configured to have an attenuation value that is adjusted in response to a second control signal, and a phase compensation value which compensates for a phase distortion in the selected gain mode, and a control circuit configured to control the selecting of the gain mode, the adjusting of the attenuation value and the phase compensation value, based on the first and second control signals.

A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.