The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

A front end circuit architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

A front end circuit architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

An envelope tracking (ET) bias circuit includes an envelope tracking (ET) bias circuit includes an envelope detection circuit, an envelope amplifier circuit, and an envelope output circuit. The envelope detection circuit is configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal. The envelope amplifier circuit is configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled. The envelope output circuit is configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal.

An envelope tracking (ET) bias circuit includes an envelope tracking (ET) bias circuit includes an envelope detection circuit, an envelope amplifier circuit, and an envelope output circuit. The envelope detection circuit is configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal. The envelope amplifier circuit is configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled. The envelope output circuit is configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal.

Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier.

Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier.

Adjustable load line amplifier circuits may comprise a power amplifier that has a signal input terminal to receive an input signal, a powered signal output terminal to be coupled to a load that has changing impedances, and a transistor array of transistor cells operatively coupled in parallel between the signal input terminal and the powered signal output terminal such that the transistor cells are independently configured to amplify the input signal present at the signal input terminal and effect a selected load line impedance of the transistor array that corresponds to at least one of the changing impedances of the load. The transistor array controller may be configured to effect the selected load line impedance by selectively activating one or more of the transistor cells and/or providing the transistor cells with a selectable operating voltage.

Adjustable load line amplifier circuits may comprise a power amplifier that has a signal input terminal to receive an input signal, a powered signal output terminal to be coupled to a load that has changing impedances, and a transistor array of transistor cells operatively coupled in parallel between the signal input terminal and the powered signal output terminal such that the transistor cells are independently configured to amplify the input signal present at the signal input terminal and effect a selected load line impedance of the transistor array that corresponds to at least one of the changing impedances of the load. The transistor array controller may be configured to effect the selected load line impedance by selectively activating one or more of the transistor cells and/or providing the transistor cells with a selectable operating voltage.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.