An apparatus is disclosed that implements temperature dependency compensation. In an example aspect, the apparatus includes an amplifier, a transformer, a compensation component, and a bias circuit. The amplifier is configured to amplify a wireless signal to produce an amplified wireless signal. The transformer, which includes an inductor, is coupled to the amplifier and is configured to condition the amplified wireless signal. The compensation component is coupled in series with the inductor. The compensation component includes a compensation transistor that is configured to operate in at least one of a positive temperature-dependence range or a negative temperature-dependence range. The bias circuit includes a bias node that is coupled to the compensation transistor. The bias circuit is configured to cause the compensation transistor to operate in the positive temperature-dependence range or the negative temperature-dependence range.

An apparatus is disclosed that implements temperature dependency compensation. In an example aspect, the apparatus includes an amplifier, a transformer, a compensation component, and a bias circuit. The amplifier is configured to amplify a wireless signal to produce an amplified wireless signal. The transformer, which includes an inductor, is coupled to the amplifier and is configured to condition the amplified wireless signal. The compensation component is coupled in series with the inductor. The compensation component includes a compensation transistor that is configured to operate in at least one of a positive temperature-dependence range or a negative temperature-dependence range. The bias circuit includes a bias node that is coupled to the compensation transistor. The bias circuit is configured to cause the compensation transistor to operate in the positive temperature-dependence range or the negative temperature-dependence range.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

A Digital Power-Amplifier (DPA) system includes a power amplifier (PA) circuit having control inputs and an output for generating output signals, and an adaptive control circuit that comprises an input interface, an output interface, a memory storing an adaptive control algorithm and a processor performing instructions based on the adaptive control algorithm in connection with the memory, wherein the input interface receives input-state signals and output signals of the DPA circuit, wherein the adaptive control algorithm determines, in response to the input-state signals and the output signals, control parameters of control signals transmitted to the control inputs from the output interface for controlling operations of the DPA circuit.

A Digital Power-Amplifier (DPA) system includes a power amplifier (PA) circuit having control inputs and an output for generating output signals, and an adaptive control circuit that comprises an input interface, an output interface, a memory storing an adaptive control algorithm and a processor performing instructions based on the adaptive control algorithm in connection with the memory, wherein the input interface receives input-state signals and output signals of the DPA circuit, wherein the adaptive control algorithm determines, in response to the input-state signals and the output signals, control parameters of control signals transmitted to the control inputs from the output interface for controlling operations of the DPA circuit.

Radio frequency (RF) amplifiers, such as power amplifiers, are provided herein. In certain configurations, an RF amplifier includes an input terminal that receives an RF input signal, an output terminal that provides an RF output signal, an injection-locked oscillator driver stage that amplifies the RF input signal to generate an injection-locked RF signal, and a stacked output stage that further amplifies the injection-locked RF signal to generate the RF output signal. The stacked output stage includes a stack of at least a first transistor and a second transistor in series with one another. Thus, the stacked output stage is operable over a wide range of supply voltage to overcome the relatively low breakdown voltages of scaled transistors. Moreover, the injection-locked oscillator driver stage provides the RF amplifier with excellent power efficiency, including in applications in which the stacked output stage operates with a supply voltage that is variable.

Radio frequency (RF) amplifiers, such as power amplifiers, are provided herein. In certain configurations, an RF amplifier includes an input terminal that receives an RF input signal, an output terminal that provides an RF output signal, an injection-locked oscillator driver stage that amplifies the RF input signal to generate an injection-locked RF signal, and a stacked output stage that further amplifies the injection-locked RF signal to generate the RF output signal. The stacked output stage includes a stack of at least a first transistor and a second transistor in series with one another. Thus, the stacked output stage is operable over a wide range of supply voltage to overcome the relatively low breakdown voltages of scaled transistors. Moreover, the injection-locked oscillator driver stage provides the RF amplifier with excellent power efficiency, including in applications in which the stacked output stage operates with a supply voltage that is variable.

Provided is a harmonic suppression method, a corresponding low-noise amplifier (20, 30, 40), and a communication terminal. In the harmonic suppression method, an isolation unit (23, 33, 43) is arranged between a harmonic suppression unit (24, 34, 44) of the low-noise amplifier (20, 30, 40) and an output match network (25, 35, 45)/input match network (21, 31, 41). The harmonic suppression unit (24, 34, 44) is isolated from the output match network (25, 35, 45)/input match network (21, 31, 41) by means of the isolation unit (23, 33, 43), so that the two are not affected or compromised by each other, and can be designed separately. In this way, the design flexibility of a signal amplification circuit is greatly improved, and the design difficulty is reduced.

Provided is a harmonic suppression method, a corresponding low-noise amplifier (20, 30, 40), and a communication terminal. In the harmonic suppression method, an isolation unit (23, 33, 43) is arranged between a harmonic suppression unit (24, 34, 44) of the low-noise amplifier (20, 30, 40) and an output match network (25, 35, 45)/input match network (21, 31, 41). The harmonic suppression unit (24, 34, 44) is isolated from the output match network (25, 35, 45)/input match network (21, 31, 41) by means of the isolation unit (23, 33, 43), so that the two are not affected or compromised by each other, and can be designed separately. In this way, the design flexibility of a signal amplification circuit is greatly improved, and the design difficulty is reduced.