Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

A low-noise amplifier is provided. The low-noise amplifier includes a first transistor configured to amplify an input signal; a second transistor which forms a cascade structure with the first transistor and configured to amplify an output signal of the first transistor; and a third transistor which forms a cascode structure together with the first transistor and configured to amplify the output signal of the first transistor, wherein a first signal including a sum of the output signal of the second transistor and the output signal of the third transistor is output to an output terminal.

A low-noise amplifier is provided. The low-noise amplifier includes a first transistor configured to amplify an input signal; a second transistor which forms a cascade structure with the first transistor and configured to amplify an output signal of the first transistor; and a third transistor which forms a cascode structure together with the first transistor and configured to amplify the output signal of the first transistor, wherein a first signal including a sum of the output signal of the second transistor and the output signal of the third transistor is output to an output terminal.

The embodiments described herein provide an amplifier device that utilizes bonding pad capacitance in an impedance matching network. In one specific embodiment, the amplifier device comprises: an amplifier formed on a semiconductor die, the amplifier including an amplifier input and an amplifier output, the amplifier configured to generate an amplified radio frequency (RF) signal at the amplifier output; and an impedance matching network coupled to the amplifier, the impedance matching network including a capacitor, where the capacitor includes a first plate, a second plate, and dielectric material between the first and second plates, where the first plate includes or is directly electrically coupled to a bond pad on the semiconductor die.

A device and method for amplifying signals is provided. The device can have an input to receive an input signal having a first desired signal on a first carrier, a second desired signal on a second carrier, and one or more interfering signals. The device can have a first carrier aggregation (CA) chain for use with the first desired signal and a second CA chain for use with the second desired signal. The first and second CA chains can be coupled to the input. The first and second CA chains can have a plurality of transconductance stages. Each of the transconductance stages can be configured as a high impedance stage or a low impedance stage. The transconductance stages can be selectively activated to incrementally adjust the transconductance, and therefore the input impedance, of each of the CA chains.