An excessive voltage rise of load voltage, caused by an impedance mismatching on a transmission path, is prevented, and high-frequency power is regenerated. A parallel impedance is connected to the transmission path during the voltage rise, thereby regenerating voltage caused by a standing wave and preventing excessive load voltage, together with enhancing energy usage efficiency. Establishing the parallel impedance for the load impedance, on the transmission path between the high-frequency amplifier circuit of the high-frequency power supply device and the high-frequency load, reduces impedance at the connecting position to prevent generation of excessive voltage on the transmission path, and high-frequency power is regenerated from the transmission path by the parallel impedance.

An excessive voltage rise of load voltage, caused by an impedance mismatching on a transmission path, is prevented, and high-frequency power is regenerated. A parallel impedance is connected to the transmission path during the voltage rise, thereby regenerating voltage caused by a standing wave and preventing excessive load voltage, together with enhancing energy usage efficiency. Establishing the parallel impedance for the load impedance, on the transmission path between the high-frequency amplifier circuit of the high-frequency power supply device and the high-frequency load, reduces impedance at the connecting position to prevent generation of excessive voltage on the transmission path, and high-frequency power is regenerated from the transmission path by the parallel impedance.

An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in in an OFF state.

A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

The embodiments described herein include amplifiers configured for use in radio frequency (RF) applications. In accordance with these embodiments, the amplifiers are implemented to generate a shaped envelope signal, and to apply the shaped envelope signal to transistor gate(s) of the amplifier to provide gate bias modulation. So configured, the shaped envelope signal may facilitate high linearity in the amplifier.

The embodiments described herein include amplifiers configured for use in radio frequency (RF) applications. In accordance with these embodiments, the amplifiers are implemented to generate a shaped envelope signal, and to apply the shaped envelope signal to transistor gate(s) of the amplifier to provide gate bias modulation. So configured, the shaped envelope signal may facilitate high linearity in the amplifier.

The present invention provides an RF power amplifier architecture which with dynamic digital control of the amplification by incorporating digitized RF input and output signal envelope data and environmental temperature sensor(s) readings into an arbitrary control algorithm implemented on a digital processor. Via the combination of digitally controlled DC/DC converter and a D/A converter, the quiescent bias of the power FET of the RF output stage can become a realization of virtually any function of the feedback and input data.

The present invention provides an RF power amplifier architecture which with dynamic digital control of the amplification by incorporating digitized RF input and output signal envelope data and environmental temperature sensor(s) readings into an arbitrary control algorithm implemented on a digital processor. Via the combination of digitally controlled DC/DC converter and a D/A converter, the quiescent bias of the power FET of the RF output stage can become a realization of virtually any function of the feedback and input data.

A limiter circuit is integrated into an RF power amplifier. The limiter circuit automatically starts adding attenuation at the input of the RF power amplifier after a predetermined input power level threshold is exceeded, thereby extending the safe input drive level to protect the amplifier. In a preferred embodiment of the invention, the limiter circuit is implemented using a pseudomorphic high electron mobility transistor (PHEMT) device or a metal semiconductor field effect transistor (MESPET) device. Diode connected transistors or Schottky diodes may also be used in the limiter circuit.