A low noise amplifier includes a first input port configured to receive a first input signal, a second input port configured to receive a second input signal, and a first amplifier stage including a first gain stage connected to the first input port and the second input port, and a first drive stage between the first gain stage and a first load circuit. The first gain stage includes a first-first gain block connected to the first input port, a first-second gain block connected to the second input port, and a first degeneration inductor between a ground terminal and a first common node of the first-first gain block and the first-second gain block. The amplifier includes a second amplifier stage including a second gain stage connected to the first input port and the second input port, and a second drive stage between the second gain stage and a second load.

A low noise amplifier is provided. The low noise amplifier includes a first transistor that receives a radio frequency (RF) signal through a control terminal, a second transistor that forms a cascode structure together with the first transistor, and receives an output signal of the first transistor through a first terminal, and a third transistor that forms a cascode structure together with the second transistor, and receives an output signal of the second transistor through the first terminal. The first to third transistors perform an amplification operation in response to application of a first power source voltage, and the first and second transistors or the first and third transistors perform an amplification operation in response to application of a second power source voltage.

A low noise amplifier is provided. The low noise amplifier includes a first transistor that receives a radio frequency (RF) signal through a control terminal, a second transistor that forms a cascode structure together with the first transistor, and receives an output signal of the first transistor through a first terminal, and a third transistor that forms a cascode structure together with the second transistor, and receives an output signal of the second transistor through the first terminal. The first to third transistors perform an amplification operation in response to application of a first power source voltage, and the first and second transistors or the first and third transistors perform an amplification operation in response to application of a second power source voltage.

A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

A current control circuit controls a bias current that is supplied to an amplifier transistor that amplifies a radio-frequency signal and includes a node, a constant current source circuit that supplies a first current to the node, and a variable current source circuit that supplies a second current to the node, based on a result of comparison between a potential of the node and a reference potential. The node outputs a control current including the first current and the second current for controlling the bias current.

Wideband power combiners and splitters are provided herein. In certain embodiments, a power combiner/splitter is implemented with a first coil connecting a first port and a second port, and a second coil connecting a third port and a fourth port. The first coil and the second coil are inductively coupled to one another. For example, the first coil and the second coil can be formed using adjacent conductive layers of a semiconductor chip, an integrated passive device, or a laminate. The power combiner/splitter further includes a fifth port tapping a center of the first coil and a sixth port tapping a center of the second coil. The fifth port and the sixth port serve to connect capacitors and/or other impedance to the center of the coils to thereby provide wideband operation.

Wideband power combiners and splitters are provided herein. In certain embodiments, a power combiner/splitter is implemented with a first coil connecting a first port and a second port, and a second coil connecting a third port and a fourth port. The first coil and the second coil are inductively coupled to one another. For example, the first coil and the second coil can be formed using adjacent conductive layers of a semiconductor chip, an integrated passive device, or a laminate. The power combiner/splitter further includes a fifth port tapping a center of the first coil and a sixth port tapping a center of the second coil. The fifth port and the sixth port serve to connect capacitors and/or other impedance to the center of the coils to thereby provide wideband operation.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

Systems and apparatuses are disclosed that include a distributed power system configured to provide power to a number of loads. The system includes power converters configured to receive DC power from a common power source, each of the plurality of power converters configured to provide DC power to a corresponding load from. Each of the power converters is positioned proximal to the corresponding load that it powers.