An amplifier may comprise first and second matching networks; first and second transistors; and a transformer including first to third inductors. Also, a gate and a source of the first transistor are connected to the first matching network, one end of the first inductor is connected to a drain of the first transistor, the other end of the first inductor is connected to a source of the second transistor, one end of the second inductor is connected to a gate of the second transistor, the other end of the second inductor is grounded, one end of the third inductor is connected to a drain of the second transistor, and the other end of the third inductor is connected to the second matching network.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

A filterless high-efficiency class D power amplifier (HEPA) exploits the phase relationships of even and odd harmonics at transistor drains of a push-pull topology to eliminate output filtering, enabling an ultra-high-efficiency, low harmonic signal. The filterless HEPA relieves the amplifier of a requirement for a power consuming filter by implementing a high-quality operational harmonic block on an output stage without output buffering. The operational harmonic block senses the voltage source radio frequency to the amplifier prior to waveform squaring and employs a harmonic canceling balun to block even harmonics (in-phase) but pass odd harmonics (180° out of phase). The sensed ideal voltage source shunts the odd-harmonic currents to ground, leaving only the fundamental current on its primary to pass to the load.

A band-switching network includes a dual-band balun and a switch network. The dual-band balun includes a first output and a second output. The switch network includes a first switch and a second switch in which an input to the first switch is coupled to the first output and an input to the second switch is coupled to the second balanced output. The dual-band balun further includes a primary coil, a first secondary coil and a second secondary coil in which the first secondary coil is coupled to the first balanced output and the second secondary coil is coupled to the second balanced output. In one embodiment, the primary coil and the first secondary coil are coupled by a first coupling factor k.sub.1, and the primary coil and the second secondary coil are coupled by a second coupling factor k.sub.2 that is different from the first coupling factor k.sub.1.

Power amplifier devices and methods for fabricating power amplifier devices containing frontside heat extraction structures are disclosed. In embodiments, the power amplifier device includes a substrate, a radio frequency (RF) power die bonded to a die support surface of the substrate, and a frontside heat extraction structure further attached to the die support surface. The frontside heat extraction structure includes, in turn, a transistor-overlay portion in direct thermal contact with a frontside of the RF power die, a first heatsink coupling portion thermally coupled to a heatsink region of the substrate, and a primary heat extraction path extending from the transistor-overlay portion to the first heatsink coupling portion. The primary heat extraction path promotes conductive heat transfer from the RF power die to the heatsink region and reduce local temperatures within a transistor channel of the RF power die during operation of the power amplifier device.

Power amplifier devices and methods for fabricating power amplifier devices containing frontside heat extraction structures are disclosed. In embodiments, the power amplifier device includes a substrate, a radio frequency (RF) power die bonded to a die support surface of the substrate, and a frontside heat extraction structure further attached to the die support surface. The frontside heat extraction structure includes, in turn, a transistor-overlay portion in direct thermal contact with a frontside of the RF power die, a first heatsink coupling portion thermally coupled to a heatsink region of the substrate, and a primary heat extraction path extending from the transistor-overlay portion to the first heatsink coupling portion. The primary heat extraction path promotes conductive heat transfer from the RF power die to the heatsink region and reduce local temperatures within a transistor channel of the RF power die during operation of the power amplifier device.

A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.