Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition.

A circuit including an amplifier having an input and an output; and a feedback path comprising a transmission line electrically coupled or electrically connected to the output and the input. A low noise amplifier including the circuit wherein the feedback path cancels noise generated in the low noise amplifier.

A circuit including an amplifier having an input and an output; and a feedback path comprising a transmission line electrically coupled or electrically connected to the output and the input. A low noise amplifier including the circuit wherein the feedback path cancels noise generated in the low noise amplifier.

A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.

A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.

A band-switching network includes a dual-band balun and a switch network. The dual-band balun includes a first output and a second output. The switch network includes a first switch and a second switch in which an input to the first switch is coupled to the first output and an input to the second switch is coupled to the second balanced output. The dual-band balun further includes a primary coil, a first secondary coil and a second secondary coil in which the first secondary coil is coupled to the first balanced output and the second secondary coil is coupled to the second balanced output. In one embodiment, the primary coil and the first secondary coil are coupled by a first coupling factor k.sub.1, and the primary coil and the second secondary coil are coupled by a second coupling factor k.sub.2 that is different from the first coupling factor k.sub.1.

A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.

A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.

One embodiment is a lower power technique to compensate for radio frequency (RF) amplifier gain and phase over temperature and part-to-part variation for particular use in phased array (PA) applications.

One embodiment is a lower power technique to compensate for radio frequency (RF) amplifier gain and phase over temperature and part-to-part variation for particular use in phased array (PA) applications.