H03F3/193

Startup circuit device, filter and receiver
11405062 · 2022-08-02 · ·

The present disclosure discloses a startup circuit device, a filter and a receiver. The startup circuit device is applicable to the filter that includes a fully-differential operational amplifier and a common-mode feedback circuit device connected in sequence. Both the first startup input terminal and the first startup output terminal are connected to a first amplification input terminal of the fully-differential operational amplifier, and both the second startup input terminal and the second startup output terminal are connected to a second amplification input terminal of the fully-differential operational amplifier. The startup circuit device is configured to adjust a received input voltage to a target voltage during startup of the fully-differential operational amplifier, and output the target voltage to the fully-differential operational amplifier, such that the fully-differential operational amplifier operates at the target voltage, and stability of the fully-differential operational amplifier during the startup can be improved effectively.

METHOD AND DEVICE FOR HIGH BANDWIDTH RECEIVER FOR HIGH BAUD-RATE COMMUNICATIONS
20220224302 · 2022-07-14 ·

An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.

SYSTEMS AND METHODS FOR WIRELESS POWER DELIVERY

Disclosed are systems configured to deliver wireless charging power to electronic devices and methods for delivering wireless charging power. In some implementations, a system can include a programmable radio-frequency generator capable of generating a beam of electromagnetic pulsed radiation and plurality of solid-state amplifiers to amplify the beam of electromagnetic pulsed radiation. The amplified beam of electromagnetic pulsed radiation can be configured to wirelessly charge electronic devices at distances greater than about 100 meters.

DUAL VOLTAGE SWITCHED BRANCH LNA ARCHITECTURE
20220278653 · 2022-09-01 ·

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

DUAL VOLTAGE SWITCHED BRANCH LNA ARCHITECTURE
20220278653 · 2022-09-01 ·

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

POWER AMPLIFIER SYSTEMS WITH NON-LINEAR ANTENNA IMPEDANCE FOR LOAD COMPENSATION
20220302935 · 2022-09-22 ·

Power amplifier systems with non-linear antenna impedance for load compensation are provided. In certain embodiments, a method of power amplification in a mobile device is provided. The method includes generating a radio frequency input signal using a transceiver, amplifying the radio frequency input signal to generate a radio frequency output signal using a power amplifier, and transmitting the radio frequency output signal using an antenna, including compensating the power amplifier for a change in output load in response to a change in signal power using a non-linear impedance versus output power characteristic of the antenna.

POWER AMPLIFIER SYSTEMS WITH NON-LINEAR ANTENNA IMPEDANCE FOR LOAD COMPENSATION
20220302935 · 2022-09-22 ·

Power amplifier systems with non-linear antenna impedance for load compensation are provided. In certain embodiments, a method of power amplification in a mobile device is provided. The method includes generating a radio frequency input signal using a transceiver, amplifying the radio frequency input signal to generate a radio frequency output signal using a power amplifier, and transmitting the radio frequency output signal using an antenna, including compensating the power amplifier for a change in output load in response to a change in signal power using a non-linear impedance versus output power characteristic of the antenna.

SEMICONDUCTOR DEVICE
20220294399 · 2022-09-15 ·

According to an embodiment, a semiconductor device includes a radio-frequency amplifier circuit, a first switch, a second switch, and a third switch. The first switch is coupled between a first node and an input end of the radio-frequency amplifier circuit. The second switch is coupled between the first node and an output end of the radio-frequency amplifier circuit. The third switch is coupled between the first node and a reference potential node. A control end of the third switch is coupled to one of the first node and the reference potential node.

Power amplifier device

A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Reference generation circuit for maintaining temperature-tracked linearity in amplifier with adjustable high-frequency gain
11456708 · 2022-09-27 · ·

Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.