A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.

Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of network equipment. When the network equipment is in an idle state, at least one power amplifier transistor is switched off according to a voltage signal.

A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of network equipment. When the network equipment is in an idle state, at least one power amplifier transistor is switched off according to a voltage signal.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.