A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

A variable gain amplifier (VGA) is provided. The VGA includes at least one amplifier circuit, at least one current-steering circuit and at least one bias voltage circuit. Each current-steering circuit is coupled to its corresponding amplifier circuit. Each bias voltage circuit is coupled to its corresponding current-steering circuit to provide a positive bias voltage to each current-steering circuit.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A variable-gain amplifier and a phased array system are provided. A variable-gain amplifier includes a cascode circuit comprising a first amplification transistor and a second amplification transistor array that are cascaded, the second amplification transistor array comprising a plurality of second amplification transistors connected in parallel and configured to output an adjustable current to an output matching network, the first amplification transistor is a common-source transistor, the plurality of second amplification transistors are common-gate transistors, or the cascode circuit is a common-emitter common-base circuit, the first amplification transistor is a common-emitter amplification circuit, and the second amplification transistor array is a common-base amplification circuit. The variable-gain amplifier further including a variable capacitor circuit coupled to the second amplification transistor array and coupled to the output matching network at first nodes.

A variable-gain amplifier and a phased array system are provided. A variable-gain amplifier includes a cascode circuit comprising a first amplification transistor and a second amplification transistor array that are cascaded, the second amplification transistor array comprising a plurality of second amplification transistors connected in parallel and configured to output an adjustable current to an output matching network, the first amplification transistor is a common-source transistor, the plurality of second amplification transistors are common-gate transistors, or the cascode circuit is a common-emitter common-base circuit, the first amplification transistor is a common-emitter amplification circuit, and the second amplification transistor array is a common-base amplification circuit. The variable-gain amplifier further including a variable capacitor circuit coupled to the second amplification transistor array and coupled to the output matching network at first nodes.

A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

A subharmonic switching digital power amplifier system includes a power amplifier core that includes at least one power amplifier operable in a power back-off region and a power supply providing at least one operating voltage to the power amplifier. Characteristically, the power amplifier is toggled at a subharmonic component of a carrier frequency (Fc) to achieve power back-off wherein the power amplifier is operated in a voltage mode or current mode driver. Multi-subharmonics can be used to further enhance the power back-off efficiency. A switching digital power amplifier system employing phase interleaving is also provided.

Systems with object detection capabilities may include a radio detection and ranging (RADAR) system. The RADAR system or other portions of the systems may include analog-to-digital converter circuitry. The analog-to-digital converter circuitry may be implemented as pipeline analog-to-digital converter circuitry having multiple stages. Each stage may include multiplying digital-to-analog converter circuitry having a sampling network and amplifier circuitry. The amplifier circuitry may be implemented as a two-stage amplifier. One or more transistors in the two-stage amplifier may receive adaptive control signals that counteract bias current changes across the one or more transistors due to supply voltage changes.