A protection circuit is provided. The protection circuit protects a power amplifier that includes a power transistor configured to receive a power voltage, and a bias circuit configured to supply a bias current to the power transistor. The protection circuit includes: a first transistor, connected between a terminal of the bias circuit and a ground, and configured to sink a first current from the terminal of the bias circuit; and a second transistor, comprising a first terminal connected to the power voltage, a second terminal connected to a control terminal of the first transistor, and a control terminal connected to a reference voltage.

A protection circuit is provided. The protection circuit protects a power amplifier that includes a power transistor configured to receive a power voltage, and a bias circuit configured to supply a bias current to the power transistor. The protection circuit includes: a first transistor, connected between a terminal of the bias circuit and a ground, and configured to sink a first current from the terminal of the bias circuit; and a second transistor, comprising a first terminal connected to the power voltage, a second terminal connected to a control terminal of the first transistor, and a control terminal connected to a reference voltage.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).

Modified forms of hemagglutinin (HA) protein including those with modified immunodominant regions and with modified maturation cleavage sites, and virus and virus-like particles containing them are disclosed.

Modified forms of hemagglutinin (HA) protein including those with modified immunodominant regions and with modified maturation cleavage sites, and virus and virus-like particles containing them are disclosed.

We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle.

We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle.

A power amplifier circuit, a transmitter, and a network device are provided. The power amplifier circuit includes N input ports, N power amplifier branches, one combiner circuit, and one output port. Each of the N input ports is connected to one power amplifier branch, each of the power amplifier branches is connected to the combiner circuit, and the combiner circuit is further connected to the output port; the N power amplifier branches and the combiner circuit are configured to perform power amplification and combining on N input signals, to generate an output signal. The N power amplifier branches include one first power amplifier branch operates in a class AB or class B operating mode, and N−1 second power amplifier branches operate in a class C operating mode with different gate bias voltages, the gate bias voltages of the N−1 second power amplifier branches become lower in order.