A semiconductor integrated circuit includes an equalizer circuit configured to amplify a signal component in a particular frequency band of an input signal on a signal path after a coupling capacitor, a sampler circuit configured to convert a first signal outputted from the equalizer circuit to a digital signal, a detector circuit configured to output a second signal based on a frequency of appearance of two values included in the digital signal, and a compensator circuit configured to compensate for a shift of a DC voltage level on the signal path after the coupling capacitor based on the second signal outputted from the detector circuit.

Inductance-capacitance (LC) resonators having different resonant frequencies, and radio frequency (RF) transistor amplifiers including the same. One usage of such LC resonators is to implement RF short/DC block circuits. A RF transistor amplifier may include a transistor on a base of the RF transistor amplifier coupled to an input and an output of the RF transistor amplifier; a first inductance-capacitance (LC) resonator comprising a first inductance and a first capacitance; and a second LC resonator comprising a second inductance and a second capacitance. The first LC resonator may be configured to resonate at a first frequency, and the second LC resonator may be configured to resonate at a second frequency different from the first frequency.

A dual-band MMIC power amplifier and method of operation to amplify frequencies in different RF bands while only requiring input drive signals at frequencies f.sub.1 and f.sub.2 in a narrow RF input band. This allows for the use of a conventional narrowband RF IC to drive the MMIC and does not require additional circuitry (e.g., a LO) on the MMIC power amplifier. The matching network of the last amplification stage is modified to pass f.sub.1 (or a harmonic thereof), reflect f.sub.2, pass a P.sup.th harmonic of f.sub.2 where P is 2 or 3 and to reflect any unused 1.sup.st, 2.sup.nd or 3.sup.rd order harmonics of f.sub.1 or f.sub.2 back into the MMIC. In response to an input signal at f.sub.1, the MMIC power amplifier amplifies and outputs a signal at f.sub.1 (or a harmonic thereof). In response to an input signal at f.sub.2 at sufficient RF power, the last amplification stage operates in compression such that the MMIC power amplifier generates the harmonics, selects the P.sup.th harmonic and outputs an amplified RF signal at P*f.sub.2.

Provided are a matching network, an antenna circuit and an electronic device. The matching network includes a first inductor, a second inductor, and a third inductor, the first inductor having two ends serving as a pair of output terminals, the second inductor having two ends serving as a first pair of input terminals, and the third inductor having two ends serving as a second pair of input terminals, where a first coupling coefficient between the first inductor and the second inductor is greater than a second coupling coefficient between the first inductor and the third inductor. According to the matching network, the matching network can present a rather large resistance value conversion ratio even with a rather small area taken by inductors, the circuit design can be more flexible, and the signal interference can be lowered.

Provided is a method of processing an input signal of an amplifier in an electronic device, the method including obtaining a pre-distorter configured to pre-distort an input signal of the amplifier by using a pretrained neural network model to pre-distort the input signal of the amplifier based on signals input to and output from the amplifier, which are obtained while the amplifier operates in a plurality of different environments, and a plurality of pieces of environmental information corresponding to the plurality of different environments, obtaining an input signal for the amplifier, obtaining information about an environment of the amplifier, pre-distorting the input signal by using the pre-distorter based on the obtained environmental information to prevent an output signal in response to the input signal to be processed by the amplifier from being distorted, and inputting the pre-distorted input signal to the amplifier.

A high-frequency amplifier includes: a common-source transistor that has gate fingers, drain fingers, and source fingers, amplifies a signal applied to each of the gate fingers as a signal to be amplified, and outputs an amplified signal from each of the drain fingers; a common-gate transistor that has source fingers connected to the drain fingers of the common-source transistor, drain fingers, and gate fingers, and amplifies the amplified signal output from each of the drain fingers of the common-source transistor; a gate bus bar connected to the gate fingers of the common-gate transistor; and capacitors each having a first end connected to the gate bus bar and a second end grounded: wherein the capacitors are arranged at respective positions where impedances obtained by looking toward the respective capacitors from the respective gate fingers of the common-gate transistor are equal to each other.

A system and method which includes receiving an input signal having an envelope and generating an envelope detection signal corresponding to the envelope. A bias current provided to an amplifier circuit is adjusted based upon the envelope detection signal, the amplifier circuit including an amplifier and a transformer. The transformer is configured to establish a magnetically coupled feedback loop from an output of the amplifier to an input of the amplifier. An output signal is provided, by the amplifier circuit, in response to the input signal.

A system and method which includes receiving an input signal having an envelope and generating an envelope detection signal corresponding to the envelope. A bias current provided to an amplifier circuit is adjusted based upon the envelope detection signal, the amplifier circuit including an amplifier and a transformer. The transformer is configured to establish a magnetically coupled feedback loop from an output of the amplifier to an input of the amplifier. An output signal is provided, by the amplifier circuit, in response to the input signal.

Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.