Patent classifications
H03F3/195
Amplifier circuitry for carrier aggregation
An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.
Amplifier circuitry for carrier aggregation
An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.
RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE
Improvement in heat dissipation capability is intended. A radio-frequency module includes a mounting substrate, a first transmission filter, a second transmission filter, a resin layer, and a shield layer. The second transmission filter is higher in power class than the first transmission filter. The resin layer covers at least part of an outer peripheral surface of the first transmission filter and covers at least part of an outer peripheral surface of the second transmission filter. The shield layer overlaps at least part of the second transmission filter in plan view in a thickness direction of the mounting substrate. At least part of a major surface of the second transmission filter on an opposite side to the mounting substrate side is in contact with the shield layer.
HIGH-FREQUENCY CIRCUIT AND COMMUNICATION DEVICE
A high-frequency circuit includes a power amplifier for a communication band A, and a power amplifier for a communication band B. Transmission in the communication band A, transmission in the communication band B, and reception in the communication band C can be simultaneously used. A frequency range of intermodulation distortion generated between a second harmonic wave of a transmission signal of the communication band A and a fundamental wave of a transmission signal of the communication band B, overlaps with at least part of a reception band of the communication band C. The power amplifier includes amplifying elements and an output trans including coils. One end of the coil is connected with an output of the amplifying element, the other end of the coil is connected with an output of the amplifying element, and one end of the coil is connected with an output terminal of the power amplifier.
TRANSISTOR WITH ODD-MODE OSCILLATION STABILIZATION CIRCUIT
A transistor includes first and second sets of gate fingers formed in an active area of a semiconductor substrate, an input bond pad formed in the semiconductor substrate and spaced apart from the active area, a first conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the first set of gate fingers, and a second conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the second set of gate fingers. A non-conductive gap is present between the distal ends of the first and second conductive structures. The transistor further includes an odd-mode oscillation stabilization circuit that includes a first resistor with a first terminal coupled to the distal end of the first conductive structure, and a second terminal coupled to the distal end of the second conductive structure.
SPDT SWITCHES WITH EMBEDDED ATTENUATORS
A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.
COMMON MODE CORRECTION USING ADC IN ANALOG PROBE BASED RECEIVER
A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
ELECTRONIC DEVICE AND METHOD INCLUDING POWER AMPLIFIER MODULE HAVING PROTECTION CIRCUIT
An electronic device includes: an antenna, a PAM including a PA configured to amplify a transmitting signal and a protection circuit, a PMIC configured to supply voltage to the PA, and at least one processor is configured to: provide a first signal, to a NAND gate in the protection circuit, provide to a AND gate in the protection circuit, a second signal indicating a result of a logical operation between the first signal and a bias enable signal for the PA, provide to the AND gate, a third signal indicating whether the transmitting signal is input to the PAM, provide to a switching circuit, a fourth signal indicating a result of logical operation between the second signal and the third signal, identify whether to apply a bias voltage to the PA based on the fourth signal, and transmit the transmitting signal, to the external electronic device, via the antenna.
POWER AMPLIFIER SYSTEM
A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.
POWER AMPLIFIER SYSTEM
A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.