Patent classifications
H03F3/195
POWER AMPLIFIER AND ELECTRONIC DEVICE INCLUDING THE SAME
The disclosure relates to a 5th generation (5G) or a pre-5G communication system for supporting a higher data transmission rate after a 4th generation (4G) communication system such as long-term evolution (LTE). A Doherty power amplifier of a wireless communication system is provided. The Doherty power amplifier includes a first power amplifier, a second power amplifier, a first transmission line connected to an output end of the first power amplifier, a second transmission line connected to an input end of the second power amplifier, a first network, and a second network, the first network may interconnect a first node connected with one end of the first transmission line and a second node connected with an output end of the second power amplifier, the one end of the first transmission line may be positioned on an opposite side with respect to the output end of the first power amplifier, and the second network may connect the first node, the second node, and a third node which is an output end of the Doherty power amplifier.
AMPLIFIER CIRCUIT FOR AMPLIFYING SINUSOID SIGNALS
Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.
UPLINK MULTIPLE INPUT-MULTIPLE OUTPUT (MIMO) TRANSMITTER APPARATUS
An uplink multiple input-multiple output (MIMO) transmitter apparatus includes a transmitter chain that includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from two original signals to be transmitted. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals match the two original signals in content but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. By employing this uplink MIMO transmitter apparatus, it is possible to use smaller power amplifiers, which may reduce footprint, power consumption, and costs of the uplink MIMO transmitter apparatus.
UPLINK MULTIPLE INPUT-MULTIPLE OUTPUT (MIMO) TRANSMITTER APPARATUS
An uplink multiple input-multiple output (MIMO) transmitter apparatus includes a transmitter chain that includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from two original signals to be transmitted. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals match the two original signals in content but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. By employing this uplink MIMO transmitter apparatus, it is possible to use smaller power amplifiers, which may reduce footprint, power consumption, and costs of the uplink MIMO transmitter apparatus.
SEMICONDUCTOR DEVICE AND POWER AMPLIFIER CIRCUIT
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.
SEMICONDUCTOR DEVICE AND POWER AMPLIFIER CIRCUIT
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.
POWER AMPLIFIER CIRCUIT
A power amplifier circuit includes first and second transistors and a first voltage output circuit. A radio frequency signal is input into a base of the first transistor. The first voltage output circuit outputs a first voltage in accordance with a power supply voltage. The first voltage is supplied to a base or a gate of the second transistor. An emitter or a source of the second transistor is connected to a collector of the first transistor. A first amplified signal generated by amplifying the radio frequency signal is output from a collector or a drain of the second transistor.
POWER AMPLIFIER CIRCUIT
A power amplifier circuit includes first and second transistors and a first voltage output circuit. A radio frequency signal is input into a base of the first transistor. The first voltage output circuit outputs a first voltage in accordance with a power supply voltage. The first voltage is supplied to a base or a gate of the second transistor. An emitter or a source of the second transistor is connected to a collector of the first transistor. A first amplified signal generated by amplifying the radio frequency signal is output from a collector or a drain of the second transistor.
BUFFER WITH INCREASED HEADROOM
Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.
SEMICONDUCTOR DEVICE AND COMMUNICATION CIRCUIT
A semiconductor device and a communication circuit capable of reducing the effect of a noise generated in an inductor are provided. A semiconductor device according to an embodiment includes a substrate, a first circuit disposed in a first area of the substrate, a second circuit disposed in a second area of the substrate, the second circuit being configured to operate selectively with the first circuit, a first inductor disposed in the second area and connected to the first circuit, and a second inductor disposed in the first area and connected to the second circuit.