An amplifier arrangement comprises N amplifier stages (10.sub.1 to 10.sub.N), wherein N is an integer equal or greater than four. The amplifier arrangement comprises a cascade of quarter wavelength transmission lines coupled between an output of an amplifier of a first amplifier stage (10.sub.1) and an output node (15) of the amplifier arrangement, wherein the cascade comprises N−1 quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). An amplifier of the Nth stage (10.sub.N) is coupled to the output node (15), and remaining amplifiers between the first and Nth stages (10.sub.2 to 10.sub.N−1) coupled to successive junctions in the cascade of quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). The amplifier arrangement is further configured such that apart from first and second amplifiers (10.sub.1 and 10.sub.2) coupled to first and second junctions of the cascade of quarter wavelength transmission lines, the remaining amplifiers (10.sub.3 to 10.sub.N) are coupled to their respective junctions of the cascade of quarter wavelength transmission lines such that successive pairs of amplifiers are either coupled via respective connecting quarter wavelength transmission lines (13) to their respective junctions, or coupled directly to their respective junctions.

An amplifier arrangement comprises N amplifier stages (10.sub.1 to 10.sub.N), wherein N is an integer equal or greater than four. The amplifier arrangement comprises a cascade of quarter wavelength transmission lines coupled between an output of an amplifier of a first amplifier stage (10.sub.1) and an output node (15) of the amplifier arrangement, wherein the cascade comprises N−1 quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). An amplifier of the Nth stage (10.sub.N) is coupled to the output node (15), and remaining amplifiers between the first and Nth stages (10.sub.2 to 10.sub.N−1) coupled to successive junctions in the cascade of quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). The amplifier arrangement is further configured such that apart from first and second amplifiers (10.sub.1 and 10.sub.2) coupled to first and second junctions of the cascade of quarter wavelength transmission lines, the remaining amplifiers (10.sub.3 to 10.sub.N) are coupled to their respective junctions of the cascade of quarter wavelength transmission lines such that successive pairs of amplifiers are either coupled via respective connecting quarter wavelength transmission lines (13) to their respective junctions, or coupled directly to their respective junctions.

Apparatus (1) comprises envelope signal amplification circuitry (11) configured to receive an input envelope signal (ENV_in) indicative of an envelope of an input radio frequency signal (RF_in) and to output an amplified envelope signal (ENV_amp); and a radio frequency power amplifier (12) configured to receive a radio frequency control signal which is dependent on the input radio frequency signal(RF_in) and the input envelope signal (ENV_in), using the amplified envelope signal (ENV_amp) as its supply voltage, to output an amplified radio frequency signal (RF_amp). A method for amplification the radio frequency signal is also provided.

A high-frequency front-end circuit includes a plurality of power amplifiers. Power supply inductors and matching inductors for the power amplifiers are formed of conductors disposed on a substrate. The power supply inductors and the matching inductors are disposed on or in different layers. When the substrate is seen in a plan view, at least a portion of the first power supply inductor and at least a portion of the second matching inductor overlap each other with an insulating layer interposed therebetween.

A high-frequency front-end circuit includes a plurality of power amplifiers. Power supply inductors and matching inductors for the power amplifiers are formed of conductors disposed on a substrate. The power supply inductors and the matching inductors are disposed on or in different layers. When the substrate is seen in a plan view, at least a portion of the first power supply inductor and at least a portion of the second matching inductor overlap each other with an insulating layer interposed therebetween.

A power amplifier circuit includes an amplifier unit disposed on a die of a semiconductor device. The amplifier unit includes an amplifier transistor. The power amplifier circuit further includes a detector transistor disposed on the die of the semiconductor device, a variable attenuator that compensates for a gain of the amplifier unit, a bias level setting holding unit that holds a bias level setting value, which is set based on at least a detection value of the detector transistor, and a bias generation unit that generates a bias value of the variable attenuator based on the bias level setting value.

A power amplifier circuit includes an amplifier unit disposed on a die of a semiconductor device. The amplifier unit includes an amplifier transistor. The power amplifier circuit further includes a detector transistor disposed on the die of the semiconductor device, a variable attenuator that compensates for a gain of the amplifier unit, a bias level setting holding unit that holds a bias level setting value, which is set based on at least a detection value of the detector transistor, and a bias generation unit that generates a bias value of the variable attenuator based on the bias level setting value.

A reconfigurable power detector is described. The reconfigurable power detector includes a first power detector circuit. The first power detector circuit includes a pair of coupled first-type transistors to switch a first-type positive output and a first-type negative output. The reconfigurable power detector includes a second power detector circuit. The second power detector circuit includes a pair of coupled second-type transistors to switch a second-type positive output and a second-type negative output. The reconfigurable power detector includes a switch matrix. The switch matrix includes switches to select the second-type positive output and the second-type negative output in a first configuration, the first-type positive output and the first-type negative output in a second configuration, and the first-type positive output and the second-type positive output in a third configuration. The reconfigurable power detector also includes a configuration block to program the switches to select an output configuration at a detector output.

A front-end module is provided. The front-end module includes a reception amplifier configured to amplify a received radio-frequency (RF) signal, first and second series switches configured to control a switching operation to electrically connect an output terminal of the reception amplifier and first and second reception ports to each other, a radio-frequency (RF) splitter configured to simultaneously transfer a received RF signal, amplified by the reception amplifier or bypassing the reception amplifier, to the first and second reception ports, first and second shunt switches configured to control a switching operation to electrically connect a ground and first and second branch nodes between the RF splitter and the first and second reception ports to each other, and first and second reflected wave removing impedance elements electrically connected between the first and second branch nodes and a ground.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.