Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Amplifiers for radio-frequency applications. In some embodiments, a power amplifier die can include a semiconductor substrate and a plurality of narrow band power amplifiers implemented on the semiconductor substrate. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.

In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier. In other embodiments shunt inductances and/or capacitors may be added to one or both amplifiers, and sized to effectively control a characteristic impedance of the impedance inverter.

A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.

The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.

Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

A MMIC support and cooling structure having a three-dimensional, thermally conductive support structure having a plurality of surfaces and a circuit having a plurality of heat generating electrical components disposed on a first portion of the surfaces and interconnected by microwave transmission lines disposed on a second portion of the plurality of surfaces of the thermally conductive support structure.

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

The present disclosure relates to a switchable power amplification structure including a first power amplifier (PA), a second PA, a front switching structure, and an end switching structure. The front switching structure is coupled to a radio frequency (RF) input port, and the end switching structure is coupled to an antenna port. Herein, the first PA and the second PA are parallel to each other, each of which is coupled between the front switching structure and the first end switching structure. The front switching structure is configured to selectively couple the first PA and the second PA to the RF input port, while the end switching structure is configured to selectively couple the first PA and the second PA to the first antenna port.