An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.

An amplification apparatus includes: a signal splitter for splitting an input radio frequency signal and outputting the resulting split radio frequency signals; a plurality of amplifier units for amplifying the radio frequency signals outputted from the signal splitter, the amplifier units being disposed circularly to form a generally cylindrical shape; a plurality of water cooling heat sinks disposed circularly at positions corresponding to the positions of the plurality of amplifier units so as to cool the plurality of amplifier units by cooling water; and a signal combiner for combining the radio frequency signals outputted from the plurality of amplifier units, respectively, and outputting the resulting combined radio frequency signal.

The present invention generally relates to a structure and method of audio amplifier by dynamic impedance adjustment, including a power amplifying unit, a loud-speaker, a current sensing unit and a subtraction unit, the power amplifying unit has a fixed closed loop gain, with an input side and an output side; the loud-speaker is electrically connected to the output side of the power amplifying unit; the current sensing unit senses the output current of the power amplifying unit, and the sensed output current is converted into a current control voltage signal; the subtraction unit inputs the audio voltage signal and the feedback current control voltage signal, and outputs the difference of the audio voltage signal minus the current control voltage signal, and inputs it to the input side of the power amplifying unit; thereby, the present invention can improve the output sound quality of the loud-speaker by dynamic impedance adjustment.

A receiver front-end circuit and an operating method thereof are disclosed. The receiver front-end circuit includes a common-mode suppression circuit and a rear-stage circuit. The common-mode suppression circuit is used to receive an external input common-mode voltage signal and perform common-mode noise suppression processing on the external input common-mode voltage signal, and then output an internal input common-mode voltage signal. The rear-stage circuit is coupled to the common-mode suppression circuit and used to receive the internal input common-mode voltage signal. The dynamic swing of the internal input common-mode voltage signal is smaller than the dynamic swing of the external input common-mode voltage signal.

Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

An example process includes reducing a quality factor of a first tunable bandpass filter, used, for example, in a low-noise amplifier stage of a polar receiver. A first wideband test signal centered at a desired center frequency of a second tunable bandpass filter is received. A frequency response of the second tunable bandpass filter to the first wideband test signal is estimated using a Fast Fourier Transform (FFT) signal processor. At least a resonant frequency or a quality factor of the second tunable bandpass filter are calibrated based at least in part on a portion of the estimated frequency response of the second tunable bandpass filter obtained from the FFT signal processor. Frequency response characteristics of the first tunable bandpass filter may be similarly tuned in accordance with the example process.

A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.

A digital power amplification circuit includes a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block including a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, a main digital power amplifier configured to receive the decoded digital codes of the first stream, an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate, an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.

High-frequency amplifier circuitry includes first amplifier circuitry, second amplifier circuitry, and noise figure improving circuitry. The first amplifier circuitry includes a first transistor and a grounded-gate third transistor. The first transistor has a source grounded via a first source inductor and a gate to which an input signal is applied. The third transistor is configured to output from a drain a signal obtained by amplifying a signal outputted from a drain of the first transistor. The second amplifier circuitry includes a same circuit constant as a circuit constant of the first amplifier circuitry and includes a second transistor and a grounded-gate fourth transistor. The noise figure improving circuitry connects the source of the first transistor and the source of the second transistor to each other.

A multi-stage device includes multiple stages such as a first stage and a second stage. During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. The transistor component is controlled to derive the output signal from the intermediate signal inputted to the circuit path.