A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

An amplifier stage uses a loaded transistor amplifier circuit including a load that causes greater second order harmonic distortion energy than third order harmonic distortion energy to be produced in said loaded transistor amplifier circuit for amplifying a source audio signal to produce an audio output signal. The spectrum of the fundamental orders of harmonic distortion is adjusted to improve perceived sound quality or listening enjoyment.

A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

A phased array element includes a transmit portion having a plurality of amplifier paths, each amplifier path having a driver amplifier and a power amplifier, a first transformer coupled to the power amplifier of a first amplifier path of the plurality of amplifier paths and a second transformer coupled to the power amplifier of a second amplifier path of the plurality of amplifier paths, a secondary winding of each of the first transformer and the second transformer coupled together by a common transformer segment, a transmit phase shifter Sswitchably coupled to the plurality of amplifier paths, a receive portion coupled to the second transformer, the receive portion having a receive path having a low noise amplifier (LNA), and a receive phase shifter coupled to the LNA.

A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.

An amplifier (300) comprising: a first signal path comprising first amplifier circuitry (105A) configured to receive a first signal (RF1) with a frequency and a variable phase and amplitude at the frequency; a second signal path comprising second amplifier circuitry (105B) configured to receive a second signal (RF2) with the frequency, wherein at least one of the relative phase and amplitude of the second signal is fixed at the frequency; combiner circuitry (106) configured to combine an output of the first amplifier circuitry and the second amplifier circuitry.

An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

An electronic device includes an antenna, a communication circuit, and a processor. The communication circuit includes a first amplifier configured to amplify a radio frequency signal; a first coupler configured to output a first amplifier output signal output from the first amplifier, to the antenna through a first port, and output at least a part of the first amplifier output signal to a first switch through a second port; and a second amplifier configured to amplify the second portion of the first amplifier output signal, output from the first switch. The processor is operably connected to the antenna and the communication circuit, wherein the processor is configured to, based on a magnitude of the first amplifier output signal, control the first switch and the second switch to use the first amplifier, or to use the first amplifier and the second amplifier.

A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.

Apparatus, systems and methods for load-adaptive 3D wireless charging are disclosed. In a 3D charging system of an example embodiment, features comprise a 3D coil design that provides magnetic field distribution coverage for a 3D charging space, e.g.

hemi-spherical space/volume; a push-pull class EF2 PA with EMI filter and transmitter circuitry that provides constant current to the 3D coil, with current direction, phase and timing control capability to adapt to load conditions; reactance shift detection circuitry comprising a voltage sensor, current sensor and phase detector and hardware for fast, real-time, computation of reactance and comparison to upper and lower limits for load-adaptive reactance tuning and for auto-protection; and a switchable tuning capacitor network arrangement of shunt and series capacitors configured for auto-tuning of input impedance, e.g. in response to a X detection trigger signal, which enables both coarse-tuning and uniform fine-tuning steps over an extended reactance range.