A technique is presented for correcting phase distortion in a digital wireless transmitter. The technique includes: receiving an RF signal in an analog domain by a digital-to-RF modulator; amplitude modulating, the RF signal in accordance with a digital input code; and introducing delay in a signal path traversed by the RF signal before the digital-to-RF modulator using a delay circuit. The duration of the delay depends upon the value of the digital input code and substantially cancels out the phase distortion introduced by the digital wireless transmitter.

A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

An envelope tracking (ET) power management circuit is provided. The ET power management circuit includes an amplifier circuit(s) configured to output a radio frequency (RF) signal at a defined power level corresponding to a direct current, an alternating current, and an ET modulated voltage received by the amplifier circuit(s). The ET power management circuit can operate in a high-power ET mode when the defined power level exceeds a defined power level threshold and the RF signal is modulated to include no more than a defined number of resource blocks. The ET power management includes two ET tracker circuitries each generating a respective ET modulated voltage and two charge pump circuitries each generating a respective current. In the high-power ET mode, both charge pump circuitries are activated to each provide a reduced current to the amplifier circuit, thus helping to reduce a footprint and cost of the ET power management circuit.

A power amplification system with shared common base biasing is disclosed. A method for power amplification at a controller of a power amplification system comprising a plurality of cascode amplifier sections can include receiving a band select signal indicative of one or more frequency bands of a radio-frequency input signal to be amplified and transmitted. The method may further include biasing a common base stage of each of the plurality of cascode amplifier sections, and biasing a common emitter stage of a subset of the plurality of cascode amplifier sections.

Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

A power amplifying device according to an embodiment includes first to fourth BTL amplifiers and first to third switch circuits. The first to fourth BTL amplifiers outputs a first to fourth output signal. The first switch circuit is turned on or off connection between an output of the second output amplifier and an output of the third output amplifier. The second switch circuit is turned on or off connection between an output of the fifth output amplifier and an output of the eighth output amplifier. The third switch circuit is turned on or off connection between an output of the fourth output amplifier and an output of the seventh output amplifier. The first to third switch circuits are turned on when the amplitudes of the first to fourth input signals are smaller than a first threshold.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

In some embodiments, a power amplification system can include a common base amplifier configured to amplify an input signal received at an input node to generate an intermediate signal at an intermediate node. The power amplification system can further include a power amplifier configured to amplify the intermediate signal received at the intermediate node to generate an output signal at an output node.

A power amplifier with supply switching is provided. The power amplifier detects a magnitude of an outgoing broadband communication signal and determines whether the magnitude exceeds a predetermined voltage threshold. The power amplifier applies a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold and a second gain using a second voltage supply rail that is smaller than the first voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold. The power amplifier produces an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain, wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected.