Systems and methods related to power amplification and power supply control. A power amplification control system can include an interface configured to receive a transceiver control signal from a transceiver. The power amplification control system can include a power amplifier control component configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver and a power supply control component configured to generate a power supply control signal based on the transceiver control signal from the transceiver and to generate the power supply control signal based on a local control signal from the power amplifier control component.

Provided is a dual-drive based Doherty amplifier that includes a first power amplifier and a second power amplifier that is in parallel with the first power amplifier. The first power amplifier is configured to receive a first portion of a signal having a first phase, and the second power amplifier is configured to receive a second portion of the signal having a second phase that has a phase difference from the first phase. At least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A Doherty amplifier circuit having a tunable impedance and phase (TIP) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance Z.sub.INV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90 (for a selected polarity)a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90 (at the selected polarity).

A distortion imparting device capable of obtaining a natural distortion effect even when output is decreased is provided. The distortion imparting device includes a first amplification part which attenuates an input audio signal on the basis of an attenuation factor set by a user and amplifies the attenuated audio signal, a second amplification part serially connected to the first amplification part, and a limiting part which is connected between an output terminal of the first amplification part and an input terminal of the second amplification part and limits an input voltage of the second amplification part to a predetermined clip voltage, wherein the limiting part determines the clip voltage on the basis of the attenuation factor.

A technique is presented for correcting phase distortion in a digital wireless transmitter. The technique includes: receiving an RF signal in an analog domain by a digital-to-RF modulator; amplitude modulating, the RF signal in accordance with a digital input code; and introducing delay in a signal path traversed by the RF signal before the digital-to-RF modulator using a delay circuit. The duration of the delay depends upon the value of the digital input code and substantially cancels out the phase distortion introduced by the digital wireless transmitter.

A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.

A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

An amplification circuit includes a first group of amplifiers including N first amplifiers, a first terminal coupled to each output of the N first amplifiers, and a second group of amplifiers including N second amplifiers. Each of the N first amplifiers and each of the N second amplifiers includes an output. The second group of amplifiers is divided into a first subassembly of amplifiers and a second subassembly of amplifiers. The first subassembly includes M second amplifiers of the second group and the second subassembly includes NM remaining second amplifiers of the second group. The amplification circuit further includes a second terminal and a third terminal. The second terminal is coupled to each output of the M second amplifiers and the third terminal is coupled to each output of the NM second remaining amplifiers.

An amplifier includes amplification stages connected in parallel between an input point and an output point and a feedback circuit, wherein the amplification stages each include a transistor configured to amplify a signal supplied from the input point, a harmonic processing unit configured to process harmonics present in an amplified signal output from an output node of the transistor, a connection point between the output node and the harmonic processing unit, and a transmission line connecting the connection point and the output point, wherein the feedback circuit feeds back a signal at the output point or a midway point of the transmission line of a given one of the amplification stages to a first end of a resistor connected to the connection point of the given one of the amplification stages, a second end of the resistor being connected to the connection point of another one of the amplification stages.