An amplifier circuit includes an output terminal, an amplification unit and a switch. The output terminal is used to output an amplification signal. The amplification unit includes a first transistor and a second transistor. The first transistor includes a control terminal for receiving a first input signal, a first terminal coupled to the output terminal for outputting an amplified first input signal, and a second terminal. The second transistor includes a control terminal for receiving a second input signal, a first terminal coupled to the output terminal for outputting an amplified second input signal, and a second terminal. The switch includes a first terminal coupled to the second terminal of the first transistor, and a second terminal. The amplification signal is generated using at least the amplified first input signal and/or the amplified second input signal.

A tunable filter reduces the total number of filters used in TDD (Time-Division Duplex) communication circuitry. The communication circuitry may include a tunable filter and a first switch associated with the tunable filter. The tunable filter may include a tuning component and a filtering component. The tuning component may be located with the first switch on a first die. The filtering component may be located in a laminate underneath the first switch. Power amplifiers for amplifying transmission signals may be located on a second die, and the second die may be located on the laminate.

Power amplification system with variable supply voltage. A power amplification system can include a power amplifier and a boost converter configured to provide a supply voltage to the power amplifier. The power amplification system can include a control system configured to provide a boost converter control signal to the boost converter to adjust the supply voltage based on a parameter associated with the power amplifier.

A stage circuit including an input unit controlling voltages of a first node and a second node by using a shift pulse or a gate start pulse input to a first input terminal, a first clock signal input to a second input terminal, a second clock signal input to a third input terminal, a first power supply input to a first power supply input terminal and a second power supply input to a second power supply input terminal, and a first output unit receiving a third clock signal from a fourth input terminal and the second power supply from the second power supply input terminal and outputting a high-level scan signal to a first output terminal corresponding to the voltages of the first node and the second node.

Spatial power-combining devices with increased output power are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each of the amplifier assemblies includes a plurality of amplifiers separately coupled to a plurality of antennas. An amplifier assembly includes a first amplifier sub-assembly and a second amplifier sub-assembly. The first amplifier sub-assembly includes a first amplifier, a first input antenna structure coupled to the first amplifier, and a first output antenna structure coupled to the first amplifier. The second amplifier sub-assembly includes a second amplifier, a second input antenna structure coupled to the second amplifier, and a second output antenna structure coupled to the second amplifier.

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

A power amplifying circuit includes a first amplifying unit that amplifies a first radio-frequency signal and a second amplifying unit that amplifies a second radio-frequency signal. The first amplifying unit includes a first matching circuit that performs impedance matching for a circuit in a preceding stage, and a first amplifying circuit that amplifies the first radio-frequency signal that has passed through the first matching circuit. The second amplifying unit includes a second matching circuit that performs impedance matching for the circuit in the preceding stage, a resistor including a first end and a second end, the first end being electrically connected to the second matching circuit, and a second amplifying circuit that is electrically connected to the second end of the resistor and that amplifies the second radio-frequency signal that has passed through the resistor.

An apparatus is disclosed including a wireless transceiver implementing transformer reconfigurability. In an example aspect, the apparatus includes a common single-ended node, a common differential node pair, and a transceiver path set. The transceiver path set includes a first transceiver path and a second transceiver path. The first transceiver path comprises a first single-ended interface and a first differential interface and includes a first transformer. The second transceiver path comprises a second single-ended interface and a second differential interface and includes a second transformer. The apparatus also includes single-ended switch circuitry and differential switch circuitry. The single-ended switch circuitry is coupled between each transceiver path of the transceiver path set and the common single-ended node. The differential switch circuitry is coupled between each transceiver path of the transceiver path set and the common differential node pair. Alternatively, an apparatus can include multiple single-ended nodes including first and second single-ended nodes.

An amplification device includes a plurality of amplifiers arranged in parallel, a plurality of directional couplers coupled to the plurality of amplifiers, respectively, and configured to receive output signals of the plurality of amplifiers, respectively, a phase shifter coupled to a first directional coupler of the plurality of directional couplers, and configured to generate a first signal to which a phase of an output signal of the first directional coupler is inverted, a combining circuit coupled to the phase shifter and a second directional coupler of the plurality of directional couplers, and configured to combine an output signal of the phase shifter and an output signal of the second directional coupler, and a processor configured to control at least one of the plurality of amplifiers so that a level of an output signal of the combining circuit is minimized.

A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.