Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

A high frequency module includes a first amplifier circuit, a second amplifier circuit, a first matching circuit connected to the first amplifier circuit, and a second matching circuit connected to the second amplifier circuit, wherein the first matching circuit and the second matching circuit are arranged adjacent to each another. The first matching circuit may be provided on an output side of the first amplifier circuit.

According to one mode of the inventive concept, an amplification device includes a first amplification unit configured to amplify an input signal when a power level of the input signal is within a first range, a second amplification unit configured to amplify the input signal when the power level of the input signal is within a second range, and an abnormality sensing unit configured to sense an occurrence of an abnormality in the second amplification unit. The abnormality sensing unit senses reverse power regarding an output of the second amplification unit to generate a sensed voltage and compares the sensed voltage with a reference voltage to sense whether an abnormality occurs in the second amplification unit.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.

An RF power amplifier includes an input coupler including a first resistor and a first capacitor, an input phase difference network of the input coupler including a first input direct current (DC) bias injection network and a second capacitor connected in series with the first resistor. The second capacitor increases a bandwidth of the RF power amplifier. The RF power amplifier may further include a first power amplifier and a second power amplifier. The first input DC bias injection network provides power to the first power amplifier and the second power amplifier. The RF power amplifier includes a lateral dimension narrower than a lateral dimension of an RF power amplifier comprising bias circuitry on two opposing sides.

An apparatus is disclosed for dual-mode amplification by varying a load impedance. In an example aspect, the apparatus includes a low-noise amplifier, a first component, a second component, and a switch. The first component has a first input impedance. The second component is coupled between the low-noise amplifier and the first component. The second component has a second input impedance that is greater than the first input impedance. The switch is coupled in parallel with the second component between the low-noise amplifier and the first component. The switch is configured to selectively be in an open state to engage the second component or a closed state to bypass the second component.

A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.