An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

A power management circuit operable to reduce rush current is provided. The power management circuit is configured to provide a time-variant voltage(s) to a power amplifier(s) for amplifying a radio frequency (RF) signal(s). Notably, a variation in the time-variant voltage(s) can cause a rush current that is proportionally related to the variation of the time-variant voltage(s). To reduce the rush current, the power management circuit is configured to maintain the time-variant voltage(s) at a non-zero standby voltage level when the power amplifier(s) is inactive. When the power amplifier(s) becomes active and the time-variant voltage(s) needs to be raised or reduced from the non-zero standby voltage level, the rush current will be smaller as a result of reduced variation in the time-variant voltage(s). As such, it is possible to prolong the battery life in a device employing the power management circuit.

A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.

A multistage linear power amplifier receiving an input signal. The multistage linear power amplifier comprises a plurality of Class-AB amplifiers connected in a cascade configuration. The plurality of Class-AB amplifiers amplifies the input signal to generate an amplified input signal. At least one of the plurality of Class-AB amplifiers is biased such that the multistage linear power amplifier emulates a Class-C amplifier.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

In a general aspect, a circuit can include an amplifier circuit including a first amplifier, a first feedback path, and a second feedback path. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier. The circuit can also include a loop circuit including a second amplifier. The loop circuit can be configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and into the negative input of the first amplifier.

An amplification unit contains two or more sets containing a plurality of amplification circuits, and amplifies power of an RF (Radio Frequency) signal. A combining unit contains two or more combiners corresponding to the two or more sets, combines RF signals output by the amplification circuits, and outputs a resultant RF signal. The amplification unit has one chassis storing each amplification circuit. The amplification unit and the combining unit have two or more connectors which are arranged transversely. The amplification unit and the combining unit are attachable/detachable.

An apparatus is disclosed for time-division duplex dynamic transceiver isolation. In an example aspect, the apparatus includes an antenna, a power amplifier circuit including at least one power-amplifying path, a low-noise amplifier, and a time-division duplex interface circuit. The interface includes at least one transmit node coupled to the at least one power-amplifying path, a receive node coupled to the low-noise amplifier, and an antenna node. The antenna node is coupled to the at least one transmit node, the receive node, and the antenna. The interface circuit is configured to connect the at least one transmit node, the receive node, and the antenna node together at both a first time and a second time. The interface circuit is configured to isolate the receive node from the antenna node at the first time and isolate the at least one transmit node from the antenna node at the second time.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.